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參數(shù)資料
| 型號： | IDT54FCT841ATD |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | FAST CMOS BUS INTERFACE LATCHES |
| 中文描述： | 快速CMOS總線接口鎖存 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 138K |
| 代理商： | IDT54FCT841ATD |
6.22
6
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
V
OH
1.5V
V
OL
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
t
PZH
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PHZ
3.5V
1.5V
0V
1.5V
ENABLE
DISABLE
V
OH
ETC.
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns
Test
Switch
Disable Low
Enable Low
Closed
All Other Tests
Open
Open Drain
DEFINITIONS:
C
L
=
Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
2571 drw 04
2571 drw 05
2571 drw 06
2571 drw 07
2571 lnk 11
2571 drw 08
相關PDF資料 |
PDF描述 |
|---|---|
| IDT54FCT841ATDB | FAST CMOS BUS INTERFACE LATCHES |
| IDT54FCT841ATE | FAST CMOS BUS INTERFACE LATCHES |
| IDT54FCT841ATEB | FAST CMOS BUS INTERFACE LATCHES |
| IDT54FCT841ATL | FAST CMOS BUS INTERFACE LATCHES |
| IDT54FCT841ATLB | FAST CMOS BUS INTERFACE LATCHES |
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