參數(shù)資料
型號: TFDU4202-TR1
廠商: Vishay Intertechnology,Inc.
英文描述: Integrated Low Profile Transceiver Module for Telecom Applications - IrDA Standard
中文描述: 集成的收發(fā)器模塊超薄電信應(yīng)用-紅外標(biāo)準(zhǔn)
文件頁數(shù): 4/13頁
文件大小: 214K
代理商: TFDU4202-TR1
www.vishay.com
4
Document Number 82541
Rev. 1.8, 05-Dec-05
TFDU4202
Vishay Semiconductors
Optoelectronic Characteristics
Receiver
Tested for the following parameters (V
CC
= 2.4 V to 5.5 V, - 25 °C to + 85 °C, unless otherwise stated).
Parameter
Test Conditions
Minimum detection threshold
irradiance (logic high receiver
input irradiance)
2.0 V, 25 °C tested
Symbol
E
e, min
Min
Typ.
25
(2.5)
Max
50
(5)
Unit
mW/m
2
(μW/cm
2
)
|
α
|
± 15 °,
V
CC
= 2.4 V to 5.5 V
E
e, min
E
e, max
50
100
mW/m
2
W/m
2
(mW/cm
2
)
W/m
2
(mW/cm
2
)
mW/m
2
(μW/cm
2
)
μW/m
2
V
Maximum detection threshold
irradiance
|
α
|
± 90 °, V
CC
= 5 V
3300
(330)
5000
(500)
|
α
|
± 90 °, V
CC
= 3 V
E
e, max
8000
(800)
15000
(1500)
Logic low receiver input
irradiance
E
e, max,low
4
(0.4)
E
e, max,low
V
OL
V
OH
Output voltage RXD
active, C = 15 pF
0
0.5
non active, C = 15 pF
V
CC
- 0.5
V
Output current RXD
V
OL
< 0.5 V
C = 15 pF, R = 2.2 k
Ω
C = 15 pF, R = 2.2 k
Ω
4
mA
Rise time at load
t
r
t
f
t
p
20
70
ns
Fall time at load
20
70
ns
RXD signal electrical output
pulse width
2.4 kbit/s, input pulse width
1.41 μs to 3/16 of bit duration
115.2 kbit/s, input pulse width
1.41 μs to 3/16 of bit duration
output level =
0.5 x V
CC
@ 40 mW/m
2
1.41
20
μs
t
p
1.41
4.5
μs
Output delay time (RXD),
leading edge optical input to
electrical output
Jitter, leading edge of output
signal
Output delay time (RXD), trailing
edge optical input to electrical
output
Power on time, SD recovery
time
Latency
t
dl
1
2
μs
over a period of 10 bit,
115.2 kbit/s
output level =
0.5 x V
CC
@ 40 mW/m
2
t
j
400
ns
t
dt
6.5
μs
0.1
1
ms
t
L
100
200
μs
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參數(shù)描述
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