參數(shù)資料
型號(hào)： IDT54FCT683AP
廠商： Integrated Device Technology, Inc.
英文描述： HIGH-PERFORMANCE CMOS BUS TRANSCEIVERS
中文描述： 高性能CMOS總線(xiàn)收發(fā)器
文件頁(yè)數(shù)： 7/8頁(yè)
文件大?。?/td> 90K
代理商： IDT54FCT683AP
IDT54/74FCT861A/B, IDT54/74FCT863A/B
HIGH-PERFORMANCE CMOS BUS TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
7.23
7
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
V
OH
1.5V
V
OL
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
t
PZH
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PHZ
3.5V
1.5V
0V
1.5V
ENABLE
DISABLE
V
OH
ETC.
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Enable Low
Closed
All Other Tests
Open
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
2610 tbl 08
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
2610 drw 03
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns
相關(guān)PDF資料
PDF描述
IDT54FCT683APB HIGH-PERFORMANCE CMOS BUS TRANSCEIVERS
IDT54FCT683ASO HIGH-PERFORMANCE CMOS BUS TRANSCEIVERS
IDT54FCT683ASOB HIGH-PERFORMANCE CMOS BUS TRANSCEIVERS
IDT54FCT683BD HIGH-PERFORMANCE CMOS BUS TRANSCEIVERS
IDT54FCT683BDB HIGH-PERFORMANCE CMOS BUS TRANSCEIVERS
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