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參數(shù)資料
| 型號： | ICS2059GI-02T |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK MULT/JITTER ATTEN 16TSSOP |
| 產(chǎn)品變化通告： | Product Discontinuation 13/May/2009 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 漂移衰減器，多路復(fù)用器 |
| PLL： | 是 |
| 輸入： | 時鐘，晶體 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 27MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 2059GI-02T |
DATASHEET
CLOCK MULTIPLIER AND JITTER ATTENUATOR
ICS2059-02
IDT / ICS CLOCK MULTIPLIER AND JITTER ATTENUATOR
1
ICS2059-02
REV E 051310
Description
The ICS2059-02 is a VCXO (Voltage Controlled Crystal
Oscillator) based clock multiplier and jitter attenuator
designed for system clock distribution applications.
This monolithic IC, combined with an external
inexpensive quartz crystal, can be used to replace a
more costly hybrid VCXO retiming module. A dual input
mux is also provided.
By controlling the VCXO frequency within a
phase-locked loop (PLL), the output clock is phase and
frequency locked to the input clock. Through selection
of external loop filter components, the PLL loop
bandwidth and damping factor can be tailored to meet
system clock requirements. A loop bandwidth down to
the Hz range is possible.
Features
Excellent jitter attenuation for telecom and video
clocks
2:1 Input MUX for input reference clocks
No switching glitches on output
VCXO-based clock generation offers very low jitter
and phase noise generation
Output clock is phase and frequency locked to the
selected input reference clock
Fixed input to output phase relationship
+115 ppm minimum crystal frequency pullability
range, using recommended crystal
Industrial temperature range
Low power CMOS technology
16-pin TSSOP package
Single 3.3 V power supply
Block Diagram
Charge
Pump
VCXO
Pullable Crystal
Selectable
Divider
Phase
Detector
ICLK1
Input Clock
ICLK2
Input Clock
ISEL
CLK
X2
X1
ISET
VDD
3
VDD
VIN
CHGP
2
GND
2
SEL1:0
0
1
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