參數(shù)資料
型號(hào)： XC5VTX240T-2FFG1759I
廠商： Xilinx Inc
文件頁數(shù)： 21/91頁
文件大小： 0K
描述： IC FPGA VIRTEX5TXT 240K 1759FBGA
產(chǎn)品培訓(xùn)模塊： PCI Express and Virtex® -5 FPGAs
標(biāo)準(zhǔn)包裝： 1
系列： Virtex®-5 TXT
LAB/CLB數(shù)： 18720
邏輯元件/單元數(shù)： 239616
RAM 位總計(jì)： 11943936
輸入/輸出數(shù)： 680
電源電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 1759-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 1759-FCBGA
配用： 568-5088-ND - BOARD DEMO DAC1408D750
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
28
Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in
Virtex-5 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are
subject to the same guidelines as the Switching Characteristics, page 30. Table 52 shows internal (register-to-register)
performance.
Table 52: Register-to-Register Performance
Description
Register-to-Register (with I/O Delays)
Units
Speed Grade
-3
-2
-1
Basic Functions
16:1 Multiplexer
550
500
450
MHz
32:1 Multiplexer
550
500
450
MHz
64:1 Multiplexer
511
467
407
MHz
9 x 9 Logic Multiplier with 4 pipe stages
468
438
428
MHz
9 x 9 Logic Multiplier with 5 pipe stages
550
500
428
MHz
16-bit Adder
550
500
450
MHz
32-bit Adder
550
500
447
MHz
64-bit Adder
423
377
323
MHz
Register to LUT to Register
550
500
450
MHz
16-bit Counter
550
500
450
MHz
32-bit Counter
550
500
450
MHz
64-bit Counter
428
381
333
MHz
Memory
Cascaded block RAM (64K)
500
450
400
MHz
Block RAM Pipelined
Single-Port 512 x 36 bits
550
500
450
MHz
Single-Port 4096 x 4 bits
550
500
450
MHz
Dual-Port A: 4096 x 4 bits and B: 1024 x 18 bits
550
500
450
MHz
Distributed RAM
Single-Port 16 x 8
550
500
450
MHz
Single-Port 32 x 8
550
500
450
MHz
Single-Port 64 x 8
550
500
450
MHz
Dual-Port 16 x 8
MHz
Shift Register Chain
16-bit
550
500
450
MHz
32-bit
550
500
450
MHz
64-bit
550
500
438
MHz
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