參數(shù)資料
型號: NAND02GW3B3BN1F
廠商: STMICROELECTRONICS
元件分類: PROM
英文描述: 256M X 8 FLASH 3V PROM, 35 ns, PDSO48
封裝: 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48
文件頁數(shù): 26/59頁
文件大?。?/td> 998K
代理商: NAND02GW3B3BN1F
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
32/59
Automatic Page 0 Read at Power-Up
The 3V devices (NANDxxxWxB) feature Automat-
ic Page 0 Read at Power-Up, which allows the mi-
crocontroller to directly download boot code from
page 0, without requiring any command or ad-
dress input sequence. The Automatic Page 0
Read feature is particularly suited for applications
that boot from the NAND.
The 1.8V devices (NANDxxxRxB) do not have the
Automatic Page 0 Read at Power-Up feature.
Automatic Page 0 Read Description. At power-
up, once the supply voltage has reached the
threshold level, VDDth, all digital outputs revert to
their reset state and the internal NAND device
functions (reading, writing, erasing) are enabled.
The PRL pin activates the Automatic Page 0 Read
function. When PRL is High at power-up, the de-
vice automatically switches to read mode where,
as in any read operation, the device is busy for a
time tBLBH1 during which data is transferred to the
Page Buffer. Once the data transfer is complete
the Ready/Busy signal goes High. The data can
then be read out sequentially on the I/O bus by
pulsing the Read Enable, R, signal.
Figure 18. shows the power-up waveforms for de-
vices featuring the Automatic Page Read option.
For details on how to order this option, refer to Ta-
Figure 18. Automatic Page 0 Read at Power-Up
Note: 1. VDDth is equal to 2.5V for 3V Power Supply devices and to 1.5V for 1.8V Power Supply devices.
VDD
W
E
AL
CL
RB
R
I/O
tBLBH1
Data1
Data2
Data3
Last
Data
Busy
Data Output
VDDth (1)
ai08665
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