參數(shù)資料
型號(hào): NAND08GR4B2BZC6T
廠商: STMICROELECTRONICS
元件分類: PROM
英文描述: 512M X 16 FLASH 1.8V PROM, 35 ns, PBGA63
封裝: 9.50 X 12 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, LFBGA-63
文件頁(yè)數(shù): 22/59頁(yè)
文件大?。?/td> 998K
代理商: NAND08GR4B2BZC6T
29/59
NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Table 13. Status Register Bits
Note: 1. The SR6 bit and SR0 bit have a different meaning during Cache Program and Cache Read operations.
2. Only valid for Cache Program operations, for other operations it is same as SR6.
3. Only valid for Cache Program operations, for other operations it is Don’t Care.
Bit
Name
Logic Level
Definition
SR7
Write Protection
'1'
Not Protected
'0'
Protected
SR6(1)
Program/ Erase/ Read
Controller
'1'
P/E/R C inactive, device ready
'0'
P/E/R C active, device busy
Cache Ready/Busy
'1'
Cache Register ready (Cache Program only)
'0'
Cache Register busy (Cache Program only)
SR5
Program/ Erase/ Read
Controller(2)
'1'
P/E/R C inactive, device ready
'0'
P/E/R C active, device busy
SR4, SR3, SR2
Reserved
Don’t Care
SR1
Cache Program Error(3)
'1'
Page N-1 failed in Cache Program operation
'0'
Page N-1 programmed successfully
SR0(1)
Generic Error
‘1’
Error – operation failed
‘0’
No Error – operation successful
Cache Program Error
‘1’
Page N failed in Cache Program operation
‘0’
Page N programmed successfully
相關(guān)PDF資料
PDF描述
NAND08GR4B3BN1 512M X 16 FLASH 1.8V PROM, 35 ns, PDSO48
NAND512R3B3BZA6E 64M X 8 FLASH 1.8V PROM, 35 ns, PBGA63
NAND512W3B3BN6E 64M X 8 FLASH 3V PROM, 35 ns, PDSO48
NAND512W3B3BZA6E 64M X 8 FLASH 3V PROM, 35 ns, PBGA63
NAND512W3B3AN1 64M X 8 FLASH 3V PROM, 35 ns, PDSO48
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