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參數(shù)資料
| 型號(hào)： | HYS72V64220GU-8 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | 3.3 V 16M x 64/72-Bit SDRAM Modules 3.3 V 32M x 64/72-Bit SDRAM Modules 3.3 V 64M x 64/72-Bit SDRAM Modules |
| 中文描述： | 64M X 72 SYNCHRONOUS DRAM MODULE, 6 ns, DMA168 |
| 封裝： | DIMM-168 |
| 文件頁(yè)數(shù)： | 8/15頁(yè) |
| 文件大小： | 274K |
| 代理商： | HYS72V64220GU-8 |
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HYS 64/72V64220GU
SDRAM-Modules
INFINEON Technologies
8
9.01
Notes
4. All AC characteristics are shown on SDRAM component level.
An initial pause of 100
μ
s is required after power-up, then a Precharge All Banks command must
be given followed by eight Auto-Refresh (CBR) cycles before the Mode Register Set Operation
can begin.
5. AC timing tests have
V
= 0.4 V and
V
= 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between
V
and
V
. All AC measurements assume
t
= 1 ns with the AC output load circuit show. Specified
t
and
t
parameters are measured
with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate
between 0.8 V and 2.0 V.
6. If clock rising time is longer than 1 ns, a time (
t
T
/2
–
0.5) ns must be added to this parameter.
7. Rated at 1.4 V
8. If
t
is longer than 1 ns, a time (
t
–
1) ns has to be added to this parameter.
9. Anytime the Refresh Period has been exceeded, a minimum of two Auto-Refresh (CBR)
commands must be given to
“
wake-up
”
the device.
10.Timing is asynchronous. If setup time is not met by rising edge of the clock then the CKE signal
is assumed latched on the next cycle.
Refresh Cycle
Refresh Period (8192 cycles)
t
REF
t
SREX
64
–
–
64
–
64
ms
6)
Self Refresh Exit Time
–
1
1
–
1
–
CLK
8)
Read Cycle
Data Out Hold Time
t
OH
t
LZ
t
HZ
t
DQZ
3
–
3
–
3
–
ns
2)
Data Out to Low Impedance
0
–
0
–
0
–
ns
–
Data Out to High Impedance
3
7
3
7
3
8
ns
9)
DQM Data Out Disable Latency
–
2
–
2
–
2
CLK
–
Write Cycle
Data Input to Precharge
(write recovery)
t
WR
2
–
2
–
2
–
CLK
–
DQM Write Mask Latency
t
DQW
0
–
0
–
0
–
CLK
–
AC Characteristics
(cont
’
d)
1), 2)
T
A
= 0 to 70
°
C;
V
SS
= 0 V;
V
DD
= 3.3 V
±
0.3 V,
t
T
= 1 ns
Parameter
Symbol
Limit Values
Unit Note
-7
PC133-222
-7.5
PC133-333
-8
PC100-222
min.
max
min.
max. min.
max.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72V64220GU-8A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| HYS72V64220GU-8B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| HYS72V64220GU-8-C2 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3 V 64M x 64/72-Bit, 512MByte SDRAM Modules 168-pin Unbuffered DIMM Modules |
| HYS72V64300GR-7.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| HYS72V64300GR-7.5-C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?512MB PC100 (2-2-2) 1-bank End-of-Life? |
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