參數(shù)資料
型號： HY5DU663222Q-7M
英文描述： DDR Synchronous DRAM
中文描述： DDR同步DRAM
文件頁數(shù)： 27/37頁
文件大?。?/td> 336K
代理商： HY5DU663222Q-7M
Rev. 0.3 / Dec. 01
27
HY5DU12422T
HY5DU12822T
HY5DU121622T
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7
IDD1 : Operating current: One bank operation
1. Typical Case : VDD = 2.5V, T=25
o
C
2. Worst Case : VDD = 2.7V, T= 10
o
C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are
changing once per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing 50% of data changing
at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
IDD7 : Operating current: Four bank operation
1. Typical Case : VDD = 2.5V, T=25
o
C
2. Worst Case : VDD = 2.7V, T= 10
o
C
3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
changing. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
相關PDF資料
PDF描述
HY5DU663222Q-8 DDR Synchronous DRAM
HY5DU12422T-L SDRAM|DDR|4X32MX4|CMOS|TSSOP|66PIN|PLASTIC
HY5DU12822ALT 64Mx8|2.5V|8K|J/M/K/H/L|DDR SDRAM - 512M
HY5DU12822AT 64Mx8|2.5V|8K|J/M/K/H/L|DDR SDRAM - 512M
HY5DU12822LT-H DDR Synchronous DRAM
相關代理商/技術參數(shù)
參數(shù)描述
HY5DU663222Q-8 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR Synchronous DRAM
HY5DV281622AT 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx16|3.3V|4K|45|DDR SDRAM - 128M
HY5DV281622AT-5 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|DDR|4X2MX16|CMOS|TSSOP|66PIN|PLASTIC
HY5DV281622DT 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(8Mx16) GDDR SDRAM
HY5DV281622DT-33 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(8Mx16) GDDR SDRAM
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