參數(shù)資料
型號： HY5DU281622DT-6
英文描述： 8Mx16|2.5V|4K|6|DDR SDRAM - 128M
中文描述： 8M × 16位|為2.5V | 4K的| 6 | DDR SDRAM內存- 128M的
文件頁數(shù)： 27/37頁
文件大小： 336K
代理商： HY5DU281622DT-6
Rev. 0.3 / Dec. 01
27
HY5DU12422T
HY5DU12822T
HY5DU121622T
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7
IDD1 : Operating current: One bank operation
1. Typical Case : VDD = 2.5V, T=25
o
C
2. Worst Case : VDD = 2.7V, T= 10
o
C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are
changing once per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing 50% of data changing
at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
IDD7 : Operating current: Four bank operation
1. Typical Case : VDD = 2.5V, T=25
o
C
2. Worst Case : VDD = 2.7V, T= 10
o
C
3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
changing. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
相關PDF資料
PDF描述
HY5DU281622T 8Mx16|2.5V|4K|H/L|DDR SDRAM - 128M
HY5DU283222F 4Mx32|2.8V|4K|26/28/33/36/4/45|DDR SDRAM - 128M
HY5DU283222Q 4Mx32|2.5V|4K|4/45/5|DDR SDRAM - 128M
HY5DU283222Q-4 SDRAM|DDR|4X1MX32|CMOS|QFP|100PIN|PLASTIC
HY5DU283222Q-45 DDR Synchronous DRAM
相關代理商/技術參數(shù)
參數(shù)描述
HY5DU281622DT-D43 制造商:SK Hynix Inc 功能描述:
HY5DU281622DT-J 制造商:SK Hynix Inc 功能描述:
HY5DU281622DT-X 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128Mb-S DDR SDRAM
HY5DU281622ET 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(8Mx16) GDDR SDRAM
HY5DU281622ET-25 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(8Mx16) GDDR SDRAM
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*