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參數資料
| 型號： | HY5DU281622AT-K |
| 英文描述： | SDRAM|DDR|4X2MX16|CMOS|TSSOP|66PIN|PLASTIC |
| 中文描述： | 內存|復員| 4X2MX16 |的CMOS | TSSOP封裝| 66PIN |塑料 |
| 文件頁數： | 25/37頁 |
| 文件大?。?/td> | 336K |
| 代理商： | HY5DU281622AT-K |
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Rev. 0.3 / Dec. 01
25
HY5DU12422T
HY5DU12822T
HY5DU121622T
DC CHARACTERISTICS II
(TA=0 to 70
°
C
, Voltage referenced to V
SS
= 0V)
64Mx8
Parameter
Symbol
Test Condition
Speed
Unit
Note
-K
-H
-L
Operating Current
IDD0
One bank; Active - Precharge ; tRC=tRC(min);
tCK=tCK(min) ; DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
changing once per clock cycle
90
90
85
Operating Current
I
DD1
One bank; Active - Read - Precharge;
Burst Length=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once per
clock cycle
120
120
110
mA
Precharge Power Down
Standby Current
I
DD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
10
mA
Idle Standby Current
I
DD2F
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs changing
once per clock cycle.
VIN=VREF for DQ, DQS and DM
35
mA
Active Power Down
Standby Current
I
DD3P
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
15
mA
Active Standby Current
I
DD3N
/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per clock
cycle; Address and other control inputs changing
once per clock cycle
50
mA
Operating Current
I
DD4R
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); IOUT=0mA
200
200
140
mA
Operating Current
I
DD4W
Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle
250
250
190
Auto Refresh Current
I
DD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz;
distributed refresh
300
300
260
Self Refresh Current
I
DD6
CKE =< 0.2V; External clock on;
tCK=tCK(min)
Normal
4
mA
Low Power
2.5
mA
Operating Current - Four
Bank Operation
I
DD7
Four bank interleaving with BL=4, Refer to the
following page for detailed test condition
400
400
300
mA
相關PDF資料 |
PDF描述 |
|---|---|
| HY5DU281622AT-L | DDR Synchronous DRAM |
| HY5DU281622DLT | 8Mx16|2.5V|4K|J/M/K/H/L|DDR SDRAM - 128M |
| HY5DU281622DT | 8Mx16|2.5V|4K|J/M/K/H/L|DDR SDRAM - 128M |
| HY5DU281622DT-6 | 8Mx16|2.5V|4K|6|DDR SDRAM - 128M |
| HY5DU281622T | 8Mx16|2.5V|4K|H/L|DDR SDRAM - 128M |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HY5DU281622AT-L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR Synchronous DRAM |
| HY5DU281622DLT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx16|2.5V|4K|J/M/K/H/L|DDR SDRAM - 128M |
| HY5DU281622DLT-X | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128Mb-S DDR SDRAM |
| HY5DU281622DT | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128Mb-S DDR SDRAM |
| HY5DU281622DT-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx16|2.5V|4K|6|DDR SDRAM - 128M |
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