參數(shù)資料
型號： HY5DU281622AT-6
英文描述： DDR Synchronous DRAM
中文描述： DDR同步DRAM
文件頁數(shù)： 30/37頁
文件大?。?/td> 336K
代理商： HY5DU281622AT-6
Rev. 0.3 / Dec. 01
30
HY5DU12422T
HY5DU12822T
HY5DU121622T
N
ote :
1.
This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2.
Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3.
For command/address input slew rate >=1.0V/ns
4.
For command/address input slew rate >=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
5.
CK, /CK slew rates are >=1.0V/ns
6.
These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by
design or tester correlation.
7.
Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.
8.
Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
Input Hold Time (slow slew rate)
t
IH
1.0
-
1.0
-
1.2
-
ns
2,4,5,6
Input Pulse Width
t
IPW
2.2
2.2
-
ns
6
Write DQS High Level Width
t
DQSH
0.35
-
0.35
-
0.35
-
CK
Write DQS Low Level Width
t
DQSL
0.35
-
0.35
-
0.35
-
CK
Clock to First Rising edge of DQS-In
t
DQSS
0.75
1.25
0.75
1.25
0.75
1.25
CK
Data-In Setup Time to DQS-In (DQ & DM)
t
DS
0.5
-
0.5
-
0.6
-
ns
6,7,
11~13
Data-in Hold Time to DQS-In (DQ & DM)
t
DH
0.5
-
0.5
-
0.6
-
ns
6,7,
11~13
DQ & DM Input Pulse Width
t
DIPW
1.75
-
1.75
-
2
-
ns
Read DQS Preamble Time
t
RPRE
0.9
1.1
0.9
1.1
0.9
1.1
CK
Read DQS Postamble Time
t
RPST
0.4
0.6
0.4
0.6
0.4
0.6
CK
Write DQS Preamble Setup Time
t
WPRES
0
-
0
-
0
-
CK
Write DQS Preamble Hold Time
t
WPREH
0.25
-
0.25
-
0.25
-
CK
Write DQS Postamble Time
t
WPST
0.4
0.6
0.4
0.6
0.4
0.6
CK
Mode Register Set Delay
t
MRD
2
-
2
-
2
-
CK
Exit Self Refresh to Any Execute Command
t
XSC
200
-
200
-
200
-
CK
8
Average Periodic Refresh Interval
t
REFI
-
7.8
-
7.8
-
7.8
us
Input Setup / Hold Slew-rate
Delta tIS
Delta tIH
V/ns
ps
ps
0.5
0
0
0.4
+50
0
0.3
+100
0
Parameter
Symbol
-K(DDR266A)
-H(DDR266B)
-L(DDR200)
Unit
Note
Min
Max
Min
Max
Min
Max
相關(guān)PDF資料
PDF描述
HY5DU281622AT-H DDR Synchronous DRAM
HY5DU281622AT-K SDRAM|DDR|4X2MX16|CMOS|TSSOP|66PIN|PLASTIC
HY5DU281622AT-L DDR Synchronous DRAM
HY5DU281622DLT 8Mx16|2.5V|4K|J/M/K/H/L|DDR SDRAM - 128M
HY5DU281622DT 8Mx16|2.5V|4K|J/M/K/H/L|DDR SDRAM - 128M
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HY5DU281622AT-H 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR Synchronous DRAM
HY5DU281622AT-K 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|DDR|4X2MX16|CMOS|TSSOP|66PIN|PLASTIC
HY5DU281622AT-L 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR Synchronous DRAM
HY5DU281622DLT 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx16|2.5V|4K|J/M/K/H/L|DDR SDRAM - 128M
HY5DU281622DLT-X 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128Mb-S DDR SDRAM
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