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參數(shù)資料
| 型號： | HW3100 |
| 廠商： | Lineage Power |
| 英文描述： | Home Phoneline Networking Chip Set(主電話線網(wǎng)絡(luò)物理層) |
| 中文描述： | 家庭電話線網(wǎng)絡(luò)芯片組（主電話線網(wǎng)絡(luò)物理層） |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 144K |
| 代理商： | HW3100 |
Lucent Technologies Inc.
5
Preliminary Product Brief
August 2000
HW3100/HW2000 Home Wire
Home Phoneline Networking Chip Set
Functional Description
(continued)
PCI
The HW3100 PCI interface is fully compliant with PCI
Local Bus Specification Revision 2.2 and the PCI
Power Management Interface Specification. PCI sub-
system ID, subvendor ID, and vendor ID are automati-
cally read from the serial EEPROM. The PCI bus
supports a 32-bit interface with an operating clock rate
between dc and 33 MHz.
HW2000 AFE Interface
The HW3100 supports a 17-pin interface to the
HW2000 AFE. The interface consists of a two-phase,
multiplexed data converter interface with control logic
used to control the positioning of the MSB of the data
as well as the internal gain or attenuation of the
HW2000 receiver and transmitter paths.
Serial EEPROM Interface
The HW3100 supports a 4-pin serial interface to exter-
nal EEPROM. The minimum serial EEPROM size is
512 bytes.
Integrated HomePNA 1.1 PHY
In order to provide backwards compatibility with exist-
ing applications and home phoneline networks based
on HomePNA1.1 technology, the HW3100 supports an
on-chip HomePNA 1.1 PHY.
The HW3100 supports a 4-pin 1M8 interface from the
integrated PHY port to the external resistive hybrid.
Media Access Controller (MAC)
The HW3100 supports an IEEE 802.3-compliant media
access controller. The MAC offloads the host CPU and
manages packet transmission, packet reception, and
destination address filtering.
JTAG Interface
The HW3100 supports an IEEE1149.1 compliant
JTAG boundary-scan test access port interface.
LSIO Interface
The HW3100 chip set supports direct connection to
either a line codec or the Silicon Labs* line codec/uni-
versal DAA.
HW2000 Overview
The HW2000 is the analog front-end for the Home Wire
chip set and provides the Home PNA 2.0 line interface
functionality. The HW2000 is composed of the following
functional blocks:
I
Integrated crystal oscillator
I
10-bit ADC and DAC
I
Variable gain amplifiers
I
Line drivers
I
Filtering
Only minimal additional components (i.e., resistive
hybrid, magnetics) are required to implement the
HomePNA2.0 line interface functionality.
Home WireChip Set: Support Tools
The primary HW3100/HW2000 Home Wire chip set
evaluation tool is the HW3100/HW2000 Home Wire
chip set PCI Reference Design. The Home WirePCI
Reference Design, bundled with drivers and installation
software, will allow quick evaluation of the Home Wire
chip set and support evaluation of interoperability.
* Silicon Labs s a registered trademark of Silicon Laboratories, Inc.
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