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參數(shù)資料
| 型號： | HM628512B |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4 M SRAM (512-kword ×8-bit)(4 M 靜態(tài)RAM(512k字×8位)) |
| 中文描述： | 四米的SRAM（512 - KWord的× 8位）（4個M靜態(tài)隨機存儲器（為512k字× 8位）） |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 88K |
| 代理商： | HM628512B |
HM628512B Series
10
Write Timing Waveform (2) (OE Low Fixed)
Low V
CC
Data Retention Characteristics (Ta =
–20 to +70
°
C)
Notes:
1.For L-version and 20
μ
A (max.) at Ta = –20 to +40
°
C.
2.For L-SL-version and 3
μ
A (max.) at Ta = –20 to +40
°
C.
3.For L-UL-version and 3
μ
A (max.) at Ta = –20 to +40
°
C.
4.CS controls address buffer, WE buffer, OE buffer, and Din buffer. In data retention mode, Vin
levels (address, WE, OE, I/O) can be in the high impedance state.
5.Typical values are at V
CC
= 3.0 V, Ta = +25
°
C and specified loading, and not guaranteed.
6.t
RC
= read cycle time.
Parameter
V
CC
for data retention
Data retention current
Symbol
V
DR
I
CCDR
Min
2
—
—
—
Typ
—
1*
5
1*
5
1*
5
Max
—
50*
1
15*
2
10*
3
Unit
V
μ
A
μ
A
μ
A
Test conditions*
4
CS
≥
V
CC
– 0.2 V, Vin
≥
0 V
V
CC
= 3.0 V, Vin
≥
0 V
CS
≥
V
CC
– 0.2 V
Chip deselect to data retention time t
CDR
Operation recovery time
0
t
RC
*
6
—
—
—
—
ns
ns
See retention waveform
t
R
Address
CS
WE
Dout
Din
t
WC
t
CW
t
WR
t
AW
t
WP
t
AS
t
WHZ
t
OW
t
OH
t
DW
t
DH
*11
*9
*10
*8
Valid Data
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| HM628512CLRR-5 | 4 M SRAM (512-kword x 8-bit) |
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| HM628512CLP-5 | 4 M SRAM (512-kword x 8-bit) |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| HM628512BFP | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4 M SRAM (512-kword x 8-bit) |
| HM628512BFP-5 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4 M SRAM (512-kword x 8-bit) |
| HM628512BFP-7 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4 M SRAM (512-kword x 8-bit) |
| HM628512BFPSERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| HM628512BI | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4 M SRAM (512-kword x 8-bit) |
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