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參數(shù)資料
| 型號： | HI5741BIB-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | DAC 14BIT 100MHZ 5.2V 28-SOIC |
| 標準包裝： | 1,000 |
| 設置時間： | 20ns |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 650mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 100M |
10
FN4071.12
September 20, 2006
Multiplying Capability
The HI5741 can operate in two different multiplying
configurations. For frequencies from DC to 100kHz, a signal
of up to 0.6VP-P can be applied directly to the REF OUT pin
as shown in Figure 22.
The signal must have a DC value such that the peak
negative voltage equals -1.25V. Alternately, a capacitor can
be placed in series with REF OUT if a DC multiplying is not
required. The lower input bandwidth can be calculated using
the following formula:
For multiplying frequencies above 100kHz, the CTRL IN pin
can be driven directly as seen in Figure 23.
The nominal input/output relationship is defined as:
In order to prevent the full scale output current from
exceeding 20.48mA, the RSET resistor must be adjusted
according to the following equation:
The circuit in Figure 23 can be tuned to adjust the lower
cutoff frequency by adjusting capacitor values. Table 1
illustrates the relationship.
Also, the input signal must be limited to 1VP-P to avoid
distortion in the DAC output current caused by excessive
modulation of the internal current sources.
Outputs
The outputs IOUT and IOUT are complementary current
outputs. Current is steered to either IOUT or IOUT in proportion
to the digital input code. The sum of the two currents is always
equal to the full scale current minus one LSB. The current
output can be converted to a voltage by using a load resistor.
Both current outputs should have the same load resistor (64
typically). By using a 64
load on the output, a 50 effective
output resistance (ROUT) is achieved due to the 227 (±15%)
parallel resistance seen looking back into the output. This is the
nominal value of the R2R ladder of the DAC. The 50
output is
needed for matching the output with a 50
line. The load
resistor should be chosen so that the effective output resistance
(ROUT) matches the line resistance. The output voltage is:
VOUT = IOUT x ROUT.
IOUT is defined in the reference section. IOUT is not trimmed to
14 bits, so it is not recommended that it be used in conjunction
with IOUT in a differential-to-single-ended application. The
compliance range of the output is from -1.25V to 0V, with a
1VP-P voltage swing allowed within this range.
Settling Time
The settling time of the HI5741 is measured as the time it
takes for the output of the DAC to settle to within a ±defined
error band of its final value during a 1/16th (code 0000... to
0001 0000.... or 1111... to 1110 1111...) scale transition. In
defining settling time specifications for the HI5741, two levels
of accuracy are considered. The accuracy levels defined for
the HI5741 are 12 (or 0.024%) and 13 (0.012%) bits.
Glitch
The output glitch of the HI5741 is measured by summing the
area under the switching transients after an update of the
DAC. Glitch is caused by the time skew between bits of the
incoming digital data. Typically, the switching time of digital
inputs are asymmetrical meaning that the turn off time is
faster than the turn on time (TTL designs). Unequal delay
paths through the device can also cause one current source
FIGURE 22. LOW FREQUENCY MULTIPLYING BANDWIDTH
CIRCUIT
REF OUT
HI5741
CIN (OPTIONAL)
0.01
F
RSET
VIN
CTRL OUT
CTRL IN
AVEE
CIN
1
2
π
() 1400
() fIN
()
-------------------------------------------
=
FIGURE 23. HIGH FREQUENCY MULTIPLYING BANDWIDTH
CIRCUIT
HI5741
CTRL IN
VIN
CTRL OUT
AVEE
200
C2
C1
50
IOUT
VIN
80
--------------
=
RSET
16VREF
IOUT Full scale
()
VIN PEAK
()
80
-----------------------------
–
------------------------------------------------------------------------------------------
=
TABLE 1. CAPACITOR SELECTION
fIN
C1
C2
100kHz
0.01
F1F
>1MHz
0.001
F0.1F
TABLE 2. INPUT CODING vs CURRENT OUTPUT
INPUT CODE (D13-D0)
IOUT (mA)
11 1111 1111 1111
-20.48
0
10 0000 0000 0000
-10.24
00 0000 0000 0000
0
-20.48
HI5741
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