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參數(shù)資料
| 型號(hào)： | HC6094IN |
| 廠(chǎng)商： | HARRIS SEMICONDUCTOR |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | ADSL Analog Front End Chip |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP44 |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大?。?/td> | 51K |
| 代理商： | HC6094IN |
1
Semiconductor
February 1999
HC6094
ADSL Analog Front End Chip
Features
14-Bit 5 MSPS DAC
Programmable Gain Stages
Anti-Aliasing and Reconstruction Filters
Applications
FDM DMT ADSL
CAP ADSL
EC DMT ADSL
Communications Receiver
Description
The HC6094 performs the Analog processing for the ADSL
chip set. The transmit chain has a 14 Bit DAC, a third-order
Chebyshev reconstruction filter and a programmable attenu-
ator (-12 to 0dB) capable of driving a 220
differential load.
The receiver chain has a high impedance input stage, pro-
grammable gain stage (0 to 24dB), additional programmable
gain (-9 to 18dB) and a third-order Chebyshev anti-aliasing
filter for driving an off-chip A/D.
Laser tri
mmable thin-film resistors are used to set the filter
cutoff frequency and DAC linearity. The transmit and receive
signal chains are specified at 65dB MTPR.
Pinout
HC6094
(MQFP)
TOP VIEW
Ordering Information
PART
NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
HC6094IN
-40 to 85
44 Ld MQFP
Q44.10x10
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17
28
27
26
25
24
23
22
21
20
19
18
39 38 37 36 35 34
33
32
31
30
29
44 43 42 41 40
VSSA_ATT
VDDA_TX
VSSA_TX
ARTN
VDDD_RX
CS
SDI
RST
SCLK
GNDD__RX
GNDA_RX
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D
R
R
V
V
P
P
P
P
R
R
D
D
V
C
G
C
C
G
V
T
T
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
Harris Corporation 1999
File Number
4260.2
[ /Title
(HC60
94)
/Sub-
ject
(ADSL
Ana-
log
Front
End
Chip)
/Autho
r ()
/Key-
words
(Har-
ris
Semi-
con-
ductor,
Tele-
com,
SLICs,
SLACs
, Tele-
phone,
Tele-
phony,
WLL,
Wire-
less
Local
Loop,
PBX,
Pri-
vate
Branch
Exchan
ge,
NT1+,
CO,
Cen-
NO REOBSOLETE PRODUCT
Call or email: centapp@harris.com
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