參數(shù)資料
型號: GS9090ACNE3
廠商: Gennum Corporation
英文描述: GS9090A GenLINX-R III 270Mb/s Deserializer for SDI
中文描述: GS9090A GenLINX - R的第三270Mb / s的SDI解串器
文件頁數(shù): 52/69頁
文件大小: 687K
代理商: GS9090ACNE3
GS9090A Preliminary Data Sheet
Proprietary and Confidential
34714 - 0
February 2006
52 of 69
Figure 3-12: Ancillary Data Extraction and Reading
%%
ANC_DATA_SWITCH = HIGH
ANC_DATA_SWITCH bit is toggled HIGH. New ancillary data is written
to second half of FIFO starting at adress zero. Application layer continues to
read from the first half of the FIFO.
Application layer
read pointer
Internal write
pointer
0
1023
1023
0
Application layer
read pointer
Internal write
pointer
0
0
1023
1023
ANC_DATA_SWITCH = LOW
0
1023
Internal write
pointer
Application layer
read pointer
ANC_DATA_SWITCH = HIGH
0
1023
ANC_DATA_SWITCH bit is toggled HIGH. New ancillary data is written to first half of
FIFO starting at address zero. Application layer continues to read from second half
of FIFO. Toggling ANC_DATA_SWITCH back LOW will clear the second half of the
FIFO and go back the situation depicted in box A.
Application layer
read pointer
Internal write
pointer
%%
0
ANC_DATA_SWITCH = LOW
1023
0
1023
ANC_DATA_SWITCH toggled LOW. First half of FIFO cleared and ancillary
data read from second half of FIFO. Device continues to write ancillary data
to second half of FIFO.
A
B
C
D
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
NOTE: At least 1100 PCLK cycles must pass between toggles of the ANC_DATA_SWITCH bit.
The bit must be toggled at a point where no extraction is occuring (i.e. the ANC signal is LOW).
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