參數(shù)資料
型號: GS9090ACNE3
廠商: Gennum Corporation
英文描述: GS9090A GenLINX-R III 270Mb/s Deserializer for SDI
中文描述: GS9090A GenLINX - R的第三270Mb / s的SDI解串器
文件頁數(shù): 26/69頁
文件大?。?/td> 687K
代理商: GS9090ACNE3
GS9090A Preliminary Data Sheet
Proprietary and Confidential
34714 - 0
February 2006
26 of 69
The ability to manually re-synchronize the flywheel is also important when
switching asynchronous sources or to implement other non-standardized video
switching functions.
The GS9090A also implements automatic switch line lock handling. By utilizing
both the synchronous switch point defined in SMPTE RP168, and the automatic
video standards detect function, the device automatically re-synchronizes the
flywheel at the switch point. This will occur whether or not the device has detected
TRS word errors. Word alignment re-synchronization will also take place at this
time.
Automatic switch line lock handling will occur regardless of the setting of the
FW_EN pin.
The switch line is as defined in
Table 3-3
.
3.6.4 HVF Timing Signal Generation
The GS9090A extracts critical timing parameters from either the received TRS
signals (FW_EN = LOW) or from the internal flywheel-timing generator (FW_EN =
HIGH).
Horizontal blanking period (H), vertical blanking period (V), and field odd / even
timing (F) are extracted and are available for output on any of the multi-function
output port pins, if so programmed (see
Programmable Multi-Function Outputs on
page 55
).
The H signal timing is configurable via the H_CONFIG bit of the internal
IOPROC_DISABLE register as either active line-based blanking, or TRS-based
blanking (see
Table 3-14
in
Error Correction and Insertion on page 42
).
The default setting of this bit (after RESET has been asserted) is LOW.
Active line-based blanking is enabled when the H_CONFIG bit is set LOW. In this
mode, the H output is HIGH for the entire horizontal blanking period, including the
EAV and SAV TRS words. This is the default H timing used by the device.
When H_CONFIG is set HIGH, TRS based blanking is enabled. In this case, the H
output will be HIGH for the entire horizontal blanking period as indicated by the H
bit in the received TRS ID words.
The timing of these signals is shown in
Figure 3-3
.
Table 3-3: Switch Line Position for 270Mb/s Digital Systems
System
Video Format
Sampling
Signal
Standard
Parallel
Interface
Serial
Interface
Switch Line
Number
525
720x483/59.94 (2:1)
4:2:2
125M
125M
259M-C
10, 273
625
720x576/50 (2:1)
4:2:2
BT.656
125M
259M-C
6, 319
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