參數(shù)資料
型號: GS9090
廠商: Gennum Corporation
英文描述: GS9090 GenLINX-R III 270Mb/s Deserializer for SDI and DVB-ASI
中文描述: GS9090 GenLINX - R的第三270Mb / s的SDI和DVB解串器,意大利航天局
文件頁數(shù): 58/70頁
文件大小: 696K
代理商: GS9090
GS9090 Data Sheet
28201 - 1
July 2005
58 of 70
3.13 GS9090 Low-latency Mode
When the IOPROC_EN pin is set LOW, the GS9090 will enter a low-latency mode
such that the parallel data will be output with the minimum PCLK latency possible.
The FIFO and all processing blocks except the descrambling and word alignment
blocks will be bypassed when SMPTE_BYPASS is HIGH.
Low-latency mode will also be selected when SMPTE_BYPASS is set LOW,
regardless of the setting of the IOPROC_EN signal (see
Table 3-20
).
In DVB-ASI mode, the device will have a higher latency than low-latency mode,
although this latency will be less than SMPTE mode.
NOTE: When in low-latency mode, the STAT pin output of the ANC packet flag is
delayed by 15 PCLK cycles with respect to the parallel video output. The length of
the flag matches the length of the ANC packet.
When the GS9090 is configured for low-latency mode, the H, V, and F output timing
will be TRS based blanking only as shown in
Figure 3-14
. Active line-based timing
is not available and the setting of the H_CONFIG host interface bit will be ignored.
Data-Through
SMPTE_BYPASS = LOW
DVB_ASI = LOW
STAT0_CONFIG
Output
High Z
000b
STAT1_CONFIG
Output
High Z
000b
STAT2_CONFIG
Output
High Z
000b
STAT3_CONFIG
Output
High Z
000b
Table 3-19: STAT [3:0] Output Default Configuration (Continued)
Device Configuration
IO_CONFIG
Register
I/O
Function
Default IO_CONFIG
Setting
Table 3-20: Pin Settings in Low-latency Mode
IOPROC_EN Setting
SMPTE_BYPASS
Setting
Latency (PCLK Cycles)
LOW
LOW
9
HIGH
LOW
10
LOW
HIGH
10
HIGH
HIGH
25
NOTE: Latency applies to parallel processing core only.
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