參數(shù)資料
型號(hào)： GS9090
廠商： Gennum Corporation
英文描述： GS9090 GenLINX-R III 270Mb/s Deserializer for SDI and DVB-ASI
中文描述： GS9090 GenLINX - R的第三270Mb / s的SDI和DVB解串器，意大利航天局
文件頁數(shù)： 54/70頁
文件大?。?/td> 696K
代理商： GS9090
GS9090 Data Sheet
28201 - 1
July 2005
54 of 70
3.10.3.2 Clearing the ANC Data FIFO
When switching to ANC FIFO mode from any other mode and on power up, the
user must follow one of the 2 methods below to ensure that the FIFO is fully
cleared.
Clearing ANC FIFO Method 1:
1. Enable ANC FIFO mode (write 10b into the FIFO_MODE register).
2. Wait for ANC_FIFO_READY bit to be asserted.
3. Toggle (LOW-to-HIGH-to-LOW) ANC_DATA_SWITCH bit (bit 12 of
IO_CONFIG register) twice.
Clearing ANC FIFO Method 2:
1. Power on device.
2. Set FIFO_EN pin HIGH.
3. Enable ANC FIFO mode (write 10b into the FIFO_MODE register).
4. Set FIFO_EN pin LOW.
5. Set FIFO_EN pin HIGH.
3.10.4 Bypass Mode
The internal FIFO is in bypass mode when the application layer sets the FIFO_EN
or IOPROC_EN pin LOW, or the FIFO_MODE[1:0] bits in the IOPROC_DISABLE
register are configured to 11b. By default, the FIFO_MODE[1:0] bits are set to 11b
by the device whenever both the SMPTE_BYPASS and DVB_ASI pins are LOW;
however, the application layer may program the FIFO_MODE[1:0] bits as required.
In bypass mode, the FIFO is not inserted into the video path and data is presented
to the output of the device synchronously with the PCLK output. The FIFO will be
disabled and placed in static mode to save power.
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