參數(shù)資料
型號(hào)： GS9035CCPJ
廠商： Gennum Corporation
英文描述： GENLINX II -TM GS9035C Serial Digital Reclocker
中文描述： GENLINX二，商標(biāo)GS9035C串行數(shù)字時(shí)鐘恢復(fù)器
文件頁(yè)數(shù)： 9/14頁(yè)
文件大小： 490K
代理商： GS9035CCPJ
GENNUM CORPORATION
20582 - 3
9 of 14
G
5.2 DVB-ASI
Design Note: For
DVB-ASI
applications having significant
instances of few bit transitions or when only K28.5 idle bits
are transmitted, the wide-band PLL in the GS9035C may
lock at 243MHz being the first 27MHz sideband below
270MHz. When normal bit density signals are transmitted,
the PLL will correctly lock onto the proper 270MHz carrier.
6. OUTPUT DATA MUTING
The GS9035C internally mutes the SDO and SDO outputs
when the device is not locked. When muted, SDO/SDO are
latched providing a logic state to the subsequent circuit
and avoiding a condition where noise could be amplified
and appear as data. The output data muting timing is
shown in Figure 12.
Fig. 12 Output Data Muting Timing
7. CLOCK ENABLE
When CLK_EN is high, the GS9035C SCO/SCO outputs are
enabled. When CLK_EN is low, the SCO/SCO outputs are
set to a high Z state and float to V
CC
. Disabling the clock
outputs results in a power savings of 10%. It is
recommended that the CLK_EN input be hard wired to the
desired state. For applications which do not require the
clock output, connect CLK_EN to Ground and connect the
SCO/SCO outputs to V
CC
.
8. STRESSFUL DATA PATTERNS
All PLL's are susceptible to stressful data patterns which
can introduce bit errors in the data stream. PLL's are most
sensitive to patterns which have long run lengths of zeros or
ones (low data transition densities for a long period of time).
The GS9035C is designed to operate with low data
transition densities such as the SMPTE 259M pathological
signal (data transition density = 0.05).
9. PLL DESIGN GUIDELINES
The performance of the GS9035C is primarily determined
by the PLL. Thus, it is important that the system designer is
familiar with the basic PLL design equations.
A model of the GS9035C PLL is shown below. The main
components are the phase detector, the VCO, and the
external loop filter components.
Fig. 13 PLL Model
9.1 Transfer Function
The transfer function of the PLL is defined as
o
/
i
and can
be approximated as
Equation 1
where
N is the divider modulus
D is the data density (=0.5 for NRZ data)
Ι
CP
is the charge pump current in Amps
K
is the VCO gain in Hz/V
This response has 1 zero (w
Z
) and three poles (w
P1
, w
BW
,
w
P2
) where
The bode plot for this transfer function is plotted in Figure 14.
LOCK
DDI
SDO
VALID
DATA
NO DATA TRANSITIONS
VALID
DATA
OUTPUTS MUTED
LOOP
FILTER
i
o
VCO
2
π
K
f
N
s
Ι
CP
R
LF
K
PD
C
LF1
C
LF2
PHASE
DETECTOR
+
-
o
i
------
sC
R
1
+
s C
LF1
R
LF
R
LF
----------
–
1
+
---------------------------------------------------------------
s
2
C
LF2
L
sR
LF
---------
1
+
+
---------------------------------------------------------
=
L
CP
-------------------
=
w
Z
LF1
LF
----------------------
=
w
P1
C
LF1
R
LF
R
LF
---------
–
--------------------------------------
=
w
BW
R
L
---------
=
w
P2
C
LF2
R
LF
----------------------
=
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