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  • 參數(shù)資料
    型號: GS864032T-250V
    廠商: GSI TECHNOLOGY
    元件分類: DRAM
    英文描述: 4M x 18, 2M x 32, 2M x 36 72Mb Sync Burst SRAMs
    中文描述: 2M X 32 CACHE SRAM, 6.5 ns, PQFP100
    封裝: TQFP-100
    文件頁數(shù): 19/23頁
    文件大小: 603K
    代理商: GS864032T-250V
    GS864018/32/36T-xxxV
    Preliminary
    Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
    Rev: 1.01 6/2006
    19/23
    2004, GSI Technology
    Sleep Mode
    During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
    the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
    low, the SRAM operates normally after 2 cycles of wake up time.
    Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I
    SB
    2. The duration of
    Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
    disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
    When the ZZ pin is driven high, I
    SB
    2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
    operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
    until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
    may be applied while the SRAM is recovering from Sleep mode.
    Sleep Mode Timing Diagram
    tZZR
    tZZH
    tZZS
    Hold
    Setup
    tKL
    tKH
    tKC
    CK
    ADSP
    ADSC
    ZZ
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