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參數(shù)資料
| 型號(hào)： | GS82032GQ-150IT |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 64K X 32 CACHE SRAM, 9 ns, PQFP100 |
| 封裝： | QFP-100 |
| 文件頁數(shù)： | 11/23頁 |
| 文件大?。?/td> | 760K |
| 代理商： | GS82032GQ-150IT |
Rev: 1.04 2/2001
19/23
2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS82032T/Q-150/138/133/117/100/66
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on
dummy cycles, and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address
boundary crossings), but greater care must be exercised to avoid excessive bus contention.
CK
ADSP
ADSC
tH
tKH tKL
tKC
tS
ZZ
tZZR
tZZH
tZZS
~ ~
Snooze
Sleep Mode Timing Diagram
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