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| 型號(hào)： | EVAL-ADN2819-CML |
| 廠(chǎng)商： | Analog Devices, Inc. |
| 元件分類(lèi)： | 限幅放大器 |
| 英文描述： | Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| 中文描述： | 多速率為2.7 Gb / s的集成時(shí)鐘和數(shù)據(jù)恢復(fù)芯片限幅放大器 |
| 文件頁(yè)數(shù)： | 4/24頁(yè) |
| 文件大小： | 570K |
| 代理商： | EVAL-ADN2819-CML |
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ADN2819
Parameter
Hysteresis (Electrical) (continued)
LOSS OF LOCK DETECTOR (LOL)
Loss of Lock Response Time
POWER SUPPLY VOLTAGE
POWER SUPPLY CURRENT
PHASE-LOCKED LOOP CHARACTERISTICS
Jitter Transfer BW
Jitter Peaking
Jitter Generation
Jitter Tolerance
CML OUTPUTS (CLKOUTP/N, DATAOUTP/N)
Single-Ended Output Swing
Differential Output Swing
Output High Voltage
Output Low Voltage
Rise Time
Fall Time
Rev. B | Page 4 of 24
Conditions
OC-3, PRBS 2
7
R
THRESH
= 2 k
R
THRESH
= 20 k
R
THRESH
= 90 k
From f
VCO
error > 1000 ppm
PIN–NIN = 10 mV p-p
OC-48
GbE
OC-12
OC-3
OC-48
OC-12
OC-3
OC-48, 12 kHz–20 MHz
OC-12, 12 kHz–5 MHz
OC-3, 12 kHz–1.3 MHz
OC-48 (See Figure 14)
600 Hz
3
6 kHz
3
100 kHz
1 MHz
3
GbE (OC-24) (See Figure 14)
300 Hz
3
3 kHz
3
50 kHz
500 kHz
3
OC-12 (See Figure 14)
30 Hz
3
300 Hz
25 kHz
250 kHz
3
OC-3 (See Figure 14)
30 Hz
3
300 Hz
3
6500 Hz
65 kHz
3
V
SE
(See Figure 7)
V
DIFF
(See Figure 7)
V
OH
V
OL
, referred to VCC
20%–80%
80%–20%
Min
5.4
4.6
3.9
3.0
150
92
20
5.5
1.0
16
16
7.7
2.2
100
44
5.8
1.0
50
23.5
6.0
1.0
300
600
–0.60
Typ
6.6
6.4
6.8
60
3.3
164
590
310
140
48
0.025
0.004
0.002
0.05
0.02
0.02
455
910
VCC
Max
7.7
8.2
9.7
3.6
215
880
480
200
85
0.003
0.09
0.002
0.04
0.002
0.04
600
1200
–0.30
150
150
Unit
dB
dB
dB
mV
V
mA
kHz
kHz
kHz
kHz
dB
dB
dB
UI rms
UI p-p
UI rms
UI p-p
UI rms
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
mV
mV
V
V
ps
ps
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