參數(shù)資料
型號: EVAL-AD7994EBZ
廠商: Analog Devices Inc
文件頁數(shù): 19/32頁
文件大小: 0K
描述: BOARD EVAL FOR AD7994
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 1
位數(shù): 12
采樣率(每秒): 188k
數(shù)據(jù)接口: 串行
輸入范圍: 0 ~ 5.5 V
在以下條件下的電源(標(biāo)準(zhǔn)): 7.7mW @ 188kSPS,5.5 V
工作溫度: -40°C ~ 125°C
已用 IC / 零件: AD7994
已供物品: 板,纜線,CD
AD7993/AD7994
Rev. 0 | Page 26 of 32
READING DATA FROM THE AD7993/AD7994
Reading data from the AD7993/AD7994 is a 1-byte or 2-byte
operation. Reading back the contents of the alert status register
or the cycle timer register is a single-byte read operation, as
shown in Figure 29. This assumes the particular register address
has previously been set up by a single-byte write operation to
the address pointer register, as shown in Figure 26. Once the
register address has been set up, any number of reads can be
performed from that particular register without having to write
to the address pointer register again. If a read from a different
register is required, the relevant register address has to be
written to the address pointer register, and again, any number of
reads from this register may then be performed.
Reading data from the configuration register, conversion result
register, DATAHIGH registers, DATALOW registers, or hysteresis
registers is a 2-byte operation, as shown in Figure 30. The same
rules apply for a 2-byte read as a 1-byte read.
When reading data back from a register on the AD7993 or the
AD7994, for example the conversion result register, if more than
two read bytes are supplied, the same or new data is read from
the AD7993/AD7994 without the need to readdress the device.
This allows the master to continuously read from a data register
without having to readdress the AD7993/AD7994.
SDA
11
99
D7
D6
D5
D2
D1
D0
R/W
A0
A1
A2
A3
0
1
SCL
D4
D3
0
03472-0-029
START BY
MASTER
ACK. BY
AD7993/AD7994
NO ACK. BY
MASTER
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
SINGLE DATA BYTE FROM AD7993/AD7994
Figure 29. Reading a Single Byte of Data from a Selected Register
SDA
11
9
ALERT
FLAG
ZERO
D10
D9
D8
A0
A1
A2
A3
0
SCL
1
D11
1
D7
D6
D5
D2
D1/0
D0/0
D4
D3
SCL (CONTINUED)
SDA (CONTINUED)
CHID1 CHID0
R/W
03472-0-030
9
START BY
MASTER
ACK. BY
AD7993/AD7994
NO ACK. BY
MASTER
ACK. BY
MASTER
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
MOST SIGNIFICANT DATA BYTE FROM
AD7993/AD7994
FRAME 2
MOST SIGNIFICANT DATA BYTE FROM
AD7993/AD7994
Figure 30. Reading Two Bytes of Data from the Conversion Result Register
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