參數(shù)資料
型號： EVAL-AD7739EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 19/32頁
文件大小： 0K
描述： BOARD EVAL FOR AD7739
標準包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 15.1k
數(shù)據(jù)接口： 串行
輸入范圍： ±2.5 V
在以下條件下的電源（標準）： 85mW @ 5V
工作溫度： -40°C ~ 105°C
已用 IC / 零件： AD7739
已供物品： 板
相關(guān)產(chǎn)品： AD7739BRUZ-REEL7-ND - IC ADC 24BIT 8CH SIG-DEL 24TSSOP
AD7739BRUZ-ND - IC ADC 24BIT 8-CH 24-TSSOP
AD7739BRU-REEL-ND - IC ADC 24BIT 8CH SIG-DEL 24TSSOP
AD7739BRU-ND - IC ADC 24BIT 8-CH 24-TSSOP
AD7739
Data Sheet
Rev. A | Page 26 of 32
MULTIPLEXER, CONVERSION, AND DATA
OUTPUT TIMING
The specified conversion time includes one or two settling and
sampling periods and a scaling time.
With chopping enabled (Figure 23), a conversion cycle starts
with a settling time of 43 MCLK cycles or 44 MCLK cycles
(~7 s with a 6.144 MHz MCLK) to allow the circuits following
the multiplexer to settle. The Σ-Δ modulator then samples the
analog signals and the digital filter processes the digital data
stream. The sampling time depends on FW, that is, on the
channel conversion time register contents. After another
settling of 42 MCLK cycles (~6.8 s), the sampling time is
repeated with a reversed (chopped) analog input signal. Then,
during the scaling time of 163 MCLK cycles (~26.5 s), the
two results from the digital filter are averaged, scaled using the
calibration registers, and written into the channel data register.
With chopping disabled (Figure 24), only one sampling time is
preceded by a settling time of 43 MCLK or 44 MCLK cycles and
followed by a scaling time of 163 MCLK cycles.
The RDY pin goes high during the scaling time, regardless of its
previous state. The relevant RDY bit is set in the ADC status
register and in the channel status register, and the RDY pin goes
low when the channel data register is updated and the channel
conversion cycle is finished. If in continuous conversion mode,
the part automatically continues with a conversion cycle on the
next enabled channel.
Note that every channel can be configured independently for
conversion time and chopping mode. The overall cycle and
effective per channel data rates depend on all enabled
channel settings.
Figure 23. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Enabled
Figure 24. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Disabled
– CHANNEL 1
SCALING
TIME
SAMPLING
TIME
+ CHANNEL 1
SAMPLING
TIME
SETTLING
TIME
MULTIPLEXER
– CHANNEL 0
RDY
SETTLING
TIME
CONVERSION TIME
03742-0-024
SCALING
TIME
CHANNEL 1
SAMPLING
TIME
MULTIPLEXER
CHANNEL 0
RDY
SETTLING
TIME
CONVERSION TIME
03742-0-025
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