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參數(shù)資料
| 型號： | EVAL-AD7298SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/25頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7298 |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，串行，SPI? |
| 工作溫度： | -40°C ~ 125°C |
| 已用 IC / 零件： | AD7298 |
| 已供物品： | 板，纜線，CD |
AD7298
Rev. B | Page 22 of 24
TEMPERATURE SENSOR READ
The temperature sensor conversion involves two phases, the
integration phase and the conversion phase as detailed in the
Temperature Sensor Operation section. The integration phase
is initiated on the falling edge of CS and once completed the
conversion is automatically initiated internally by the AD7298.
When a temperature conversion integration is initiated, the
TSENSE_BUSY signal goes high to indicate that a temperature
conversion is in progress and remains high until the conversion
is completed.
The total time to measure and convert a temperature channel
with the AD7298 is 100 μs max. Once the TSENSE_BUSY signal
goes low to indicate that the temperature conversion is
completed, 100 ns must elapse prior to the next falling edge
of CS. If a minimum of 100 ns is not adhered to between the
falling edge of TSENSE_BUSY and the subsequent falling edge of
CS, the next conversion will be corrupted but the temperature
result that is framed by the CS will not be affected. This
restriction is in place to ensure that sufficient acquisition time
is allowed for the next conversion.
Once the TSENSE_BUSY signal goes high, the user may provide a
CS falling edge to frame the read of the previous conversion and
program the control register if required (see
).
Once the previous conversion result has been read, any
subsequent CS falling edges which occur while the TSENSE_BUSY
signal is high are internally ignored by the AD7298. If addi-
tional CS falling edges are provided while TSENSE_BUSY is high,
the AD7298 provides an invalid digital output of all 1s.
Alternatively, if CS remains high while TSENSE_BUSY is high,
then the DOUT bus remains in three-state.
If the user writes to the control register during the first 16 SCLK
cycles following TSENSE_BUSY going high, the configuration of
the device for the next conversion, which is initiated on the
subsequent CS falling edge after TSENSE_BUSY goes low, is
altered. If the user configures the part for partial power-down in
a write to the control register during the first 16 SCLK cycles
following TSENSE_BUSY going high, the temperature sensor
conversion is aborted and the part enters partial power-down
on the 16th SCLK falling edge.
Thus, it is recommended not to write to the control register if
the CS signal will be toggling while TSENSE_BUSY is high. Care
should be taken to ensure that the WRITE bit is set to zero
during the temperature conversion phase when CS is toggling.
If an SCLK frequency of more than 10 kHz is used, the
temperature conversion requires more than one standard
read cycle to complete. In this case, the user can monitor the
TSENSE_BUSY signal to determine when the conversion is
completed and the result is available for reading.
CS
SCLK
DOUT
DIN
112
16
1
16
1
16
TEMPERATURE SENSOR RESULT
PREVIOUS CONVERSION
RESULT
CONFIGURE CONTROL REGISTER
FOR NEXT CONVERSION
DATA WRITTEN TO CONTROL
REGISTER CH TSENSE SELECTED
TSENSE_BUSY
THE TEMPERATURE
CONVERSION IS COMPLETED
t11
THE TEMPERATURE
INTEGRATION BEGINS
ENSURES ADEQUATE ACQUISITION
TIME FOR NEXT ADC CONVERSION
08
754
-015
Figure 31. Serial Interface Timing Diagram for the Temperature Sensor Conversion
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