參數(shù)資料
型號(hào)： EVAL-AD7150EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/28頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD7150
特色產(chǎn)品： AD715x Series Capacitance-to-Digital Converters & Evaluation Board
標(biāo)準(zhǔn)包裝： 1
傳感器類型： 觸摸，電容式
接口： I²C
電源電壓： 2.7 V ~ 3.6 V
嵌入式： 否
已供物品： 板，電池
已用 IC / 零件： AD7150
產(chǎn)品目錄頁(yè)面： 781 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： AD7150BRMZ-REEL-ND - IC CAP CONV 2CH ULT LP 10MSOP
AD7150BRMZ-ND - IC CAP CONV 2CH ULT LP 10MSOP
AD7150
Rev. 0 | Page 17 of 28
TIMEOUT REGISTERS
When either the approaching or receding timeout elapses (that
is, after the defined number of CDC conversions is counted),
the data average (and thus the thresholds) is forced to follow the
new CDC data value immediately.
Ch1 Address Pointer 0x0A
Ch2 Address Pointer 0x0D
8 Bits, Read/Write, Factory Preset 0x86
When the timeout register equals 0, timeouts are disabled.
Table 9. Timeout Register Bit Map
Bit
Bits [7:4]
Bits [3:0]
Mnemonic
TimeOutApr
TimeOutRec
Default
0x08
0x06
DATA AVERAGE
+ SENSITIVITY
LARGE CHANGE IN DATA
TOWARDS THRESHOLD
DATA AVERAGE
THRESHOLD
TIME
TIMEOUT APPROACHING
06
51
7-
0
4
7
These registers set timeouts for the adaptive threshold mode.
The approaching timeout starts when the CDC data crosses the
data average ± sensitivity band toward the threshold, according
to the selected positive, negative, or window threshold mode.
The approaching timeout elapses after the number of conversion
cycles equals 2TimeOutApr, where TimeOutApr is the value of the four
most significant bits of the timeout register.
Figure 39. Threshold Timeout Approaching
After a Large Change in CDC Data Toward Threshold
DATA AVERAGE
+ SENSITIVITY
LARGE CHANGE IN DATA
AWAY FROM THE THRESHOLD
DATA AVERAGE
THRESHOLD
TIME
TIMEOUT RECEDING
06
51
7-
0
48
The receding timeout starts when the CDC data crosses the
data average ± sensitivity band away from the threshold,
according to the selected positive or negative threshold mode.
The receding timeout is not used in the window threshold
mode. The receding timeout elapses after the number of
conversion cycles equals 2TimeOutRec, where TimeOutRec is the
value of the four least significant bits of the timeout register.
Figure 40. Threshold Timeout Receding
After a Large Change in CDC Data Away from Threshold
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