參數(shù)資料
型號(hào)： EVAL-AD7150EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/28頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD7150
特色產(chǎn)品： AD715x Series Capacitance-to-Digital Converters & Evaluation Board
標(biāo)準(zhǔn)包裝： 1
傳感器類型： 觸摸，電容式
接口： I²C
電源電壓： 2.7 V ~ 3.6 V
嵌入式： 否
已供物品： 板，電池
已用 IC / 零件： AD7150
產(chǎn)品目錄頁(yè)面： 781 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： AD7150BRMZ-REEL-ND - IC CAP CONV 2CH ULT LP 10MSOP
AD7150BRMZ-ND - IC CAP CONV 2CH ULT LP 10MSOP
AD7150
Rev. 0 | Page 22 of 28
If a repeated start condition is encountered after the address
pointer byte, all peripherals connected to the bus respond
exactly as outlined previously for a start condition; that is, a
repeated start condition is treated the same as a start condition.
When a master device issues a stop condition, it relinquishes
control of the bus, allowing another master device to take
control of the bus. Therefore, a master wanting to retain control
of the bus issues successive start conditions known as repeated
start conditions.
AD7150 RESET
To reset the AD7150 without having to reset the entire serial
bus, an explicit reset command is provided. This uses a particular
address pointer word as a command word to reset the part and
upload all default settings. The AD7150 does not respond to the
serial bus commands (do not acknowledge) during the default
values upload for approximately 2 ms.
The reset command address word is 0xBF.
GENERAL CALL
When a master issues a slave address consisting of seven 0s with
the eighth bit (R/W bit) set to 0, this is known as the general call
address. The general call address is for addressing every device
connected to the serial bus. The AD7150 acknowledges this
address and reads in the following data byte.
If the second byte is 0x06, the AD7150 is reset, completely
uploading all default values. The AD7150 does not respond to
the serial bus commands (do not acknowledge) during the
default values upload for approximately 2 ms.
The AD7150 does not acknowledge any other general call
commands.
1–7
8
9
1–7
8
9
1–7
8
9
P
S
START ADDR R/W ACK SUBADDRESS ACK
DATA
ACK
STOP
SDATA
SCLOCK
0
65
17
-05
0
Figure 42. Bus Data Transfer
DATA
A(S)
S SLAVE ADDR A(S)
SUB ADDR
A(S)
LSB = 0
LSB = 1
DATA
P
S SLAVE ADDR A(S)
SUB ADDR A(S) S SLAVE ADDR
A(S)
DATA
A(M)
DATA
P
WRITE
SEQUENCE
READ
SEQUENCE
A(S) = NO ACKNOWLEDGE BY SLAVE
A(M) = NO ACKNOWLEDGE BY MASTER
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
S = START BIT
P = STOP BIT
A(S)
A(M)
065
17
-05
1
Figure 43. Write and Read Sequences
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