
ESS Technology, Inc.
SAM0241-052101
3
ES4408 PRODUCT BRIEF
ES4408 PIN DESCRIPTION
ES4408 PIN DESCRIPTION
Table 1 lists the pin descriptions for the ES4408.
Table 1 ES4408 Pin Descriptions
Name
VCC
Number
I/O
I
Definition
3.65 V ± 150 mv.
1, 9, 18, 27, 35, 44,
51, 59, 68, 75, 83,
92, 99, 104, 111,
121, 130, 139, 148,
157, 164, 172, 183,
193, 201
23:19, 16:10, 7:2,
207:204
8, 17, 26, 34, 43, 52,
60, 67, 76, 84, 91,
98, 103, 112, 120,
129, 138, 147, 156,
163, 171, 177, 184,
192, 200, 208
24
25
LA[21:0]
O
Device address output.
VSS
I
Ground.
RESET#
TDMDX
RSEL
I
Reset input, active low.
TDM transmit data.
ROM Select
RSEL
0
1
O
I
TDMDR
TDMCLK
TDMFS
TDMTSC#
TWS
SEL_PLL[2:0]
28
29
30
31
32
33
I
I
I
TDM receive data.
TDM clock input.
TDM frame sync.
TDM output enable, active low.
Audio transmit frame sync.
Select PLL1.
SEL_PLL2 SEL_PLL0 Clock Output
0
0
1
1
O
O
I
TSD[3:0]
MCLK
TBCK
SPDIF_DOBM
RSD
RWS
RBCK
APLLCAP
XIN
XOUT
DMA[11:0]
DCAS#
DOE#
DSCK_EN
DWE#
DRAS[2:0]#
DB[15:0]
DCS[1:0]#
38,37,36,33
39
40
41
45
46
47
48
49
50
66:61, 58:53
69
70
O
I/O
I/O
O
I
I
I
I
I
O
O
O
O
I
O
O
I/O
O
Audio transmit serial data port.
Audio master clock for audio DAC.
Audio transmit bit clock.
S/PDIF (IEC958) Format Output.
Audio receive serial data.
Audio receive frame sync.
Audio receive bit clock.
Analog PLL Capacitor.
Crystal input.
Crystal output.
DRAM address bus.
Column address strobe, active low.
Output enable, active low.
Clock Enable, active low.
DRAM write enable, active low.
Row address strobe, active low.
DRAM data bus.
SDRAM chip select [1:0], active low.
71
74:72
96:93, 90:85, 82:77
97,100
Selection
8-bit ROM
16-bit ROM
0
1
0
1
2.5 x DCLK
3 x DCLK
3.5 x DCLK
4 x DCLK