
24
Altera Corporation
Errata Sheet - Appendix A
It is therefore possible to determine where external stall cycles have been
inserted, and to count forward 6 cycles from that point to find where they
should have been inserted, not counting other external stall cycles. This is
a complex procedure which cannot easily be automated, and cannot be
regarded as a complete workaround.
Table 7
shows an example of this technique. Note that, as in
Table 6
, the
trace reports stall cycles before the corresponding instruction is traced, not
after.
Table 7. Example of how to calculate the correct location of a stall (Part 1 of 2)
Cycle
Address
Instruction
Actual trace
Reconstructed
trace
Notes
600
601
602
2000
2004
MOV r1,r0
LDR r2,var0
(interlock on r2)
This is an internal stall and can
be predicted
603
604
605
2008
200C
ADD r2,r2,#1
B 2018
(Branch delay)
These cycles are also
predictable internal stalls
606
607
608
609
(Branch delay)
ADD r2,r2,#1
LDR r3,var1
(LDR stalled)
2018
201C
An external stall
610
2020
LDR r4,var2
IE (instruction
executed) for 2000
IE for 2000
611
2024
ADD r2,r2,#1
WT (wait)
WT
Only one stall was predicted for 2004.
One must be an external stall.
Counting forward 6 from the first puts
it on 2018, the second on 201C.
Remove it and try to place later.
612
WT
IE for 2004
613
IE for 2004
IE for 2008
614
IE for 2008
WT
615
WT
WT
616
WT
IE for 200C
617
IE for 200C
IE for 2018
The stall could correspond to 2018 in
theory, but in this system only the
memory system can cause external
stalls, and the code is in fast
instruction memory, so an ADD could
not cause an external stall.