- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362754 > EPVP6200 (ELAN Microelctronics Corp .) VFD Controller PDF資料下載
參數(shù)資料
| 型號： | EPVP6200 |
| 廠商： | ELAN Microelctronics Corp . |
| 英文描述： | VFD Controller |
| 中文描述： | 變頻控制器 |
| 文件頁數(shù)： | 28/57頁 |
| 文件大?。?/td> | 442K |
| 代理商： | EPVP6200 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當(dāng)前第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁
ePVP6200
VFD Controller
22 of 57
11.18.2004 (V1.53)
This specification is subject to change without further notice.
Bit 3 (PAB)
:
Prescaler assignment bit
0/1
TCC/WDT
When in WDT mode (Bit 3 = 1), the prescaler is cleared by the WDTC and
SLEP instructions. Likewise, when in TCC mode (Bit 3 = 0), the prescaler
will can NOT be cleared by SLEP instructions.
An 8-bit counter is provided as prescaler for the TCC or WDT. The
prescaler is available for the TCC only or for the WDT only at a given time.
An 8 bit counter is made available for TCC or WDT as determined by the
status of Bit 3 (PAB) of the CONT register.
Both TCC and prescaler are cleared each time a write to TCC instruction is
executed. (See the table above for the prescaler ratio under CONT register
and Fig.7 below for the TCC/WDT block diagram.)
Bit 4 (RETBK)
:
Return value backup control for interrupt routine
0/1
disable/enable
When this bit is set to 1, the CPU will store ACC, R3 status, and R5 PAGE 1
automatically after an interrupt is triggered. It will be restored after
instruction RETI. When this bit is set to 0, you need to store ACC, R3, and
R5 PAGE 1 in you program.
Bit 5 (TS)
:
TCC signal source
0
internal instruction cycle clock
timing = ( 2 / system clock) * prescaler* (256 – count vaule)
1
16.384kHz
iming = ( 1 /16.384k) * prescaler * (256 – count vaule)
Bit 6 (INT)
:
INT enable flag
0
interrupt masked by DISI or hardware interrupt
1
interrupt enabled by ENI/RETI instructions
Bit 7 (P90EG)
:
Interrupt edge type of P90
0
P90 interruption source is a rising edge signal.
1
P90 interruption source is a falling edge signal.
16.38KHz
Fig. 7 TCC & WDT Block Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EPVP6300 | VFD Controller |
| EPVP6800 | VFD Controller |
| EPVP6810 | VFD Controller |
| EPXA4 | Excalibur Devices |
| EPZ3001G | Power Choke |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPVP6300 | 制造商:EMC 制造商全稱:ELAN Microelectronics Corp 功能描述:VFD Controller |
| EPVP6800 | 制造商:EMC 制造商全稱:ELAN Microelectronics Corp 功能描述:VFD Controller |
| EPVP6810 | 制造商:EMC 制造商全稱:ELAN Microelectronics Corp 功能描述:VFD Controller |
| EPWB400 | 制造商:Electrolube 功能描述:PAINT, WHITE GLOSS 400ML |
| EPWR30 | 制造商:Black Box Corporation 功能描述:ALL-WEATHER SINGLE OUTLETORANG |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。