參數(shù)資料
型號(hào): EPVP6200
廠商: ELAN Microelctronics Corp .
英文描述: VFD Controller
中文描述: 變頻控制器
文件頁數(shù): 22/57頁
文件大小: 442K
代理商: EPVP6200
ePVP6200
VFD Controller
16 of 57
11.18.2004 (V1.53)
This specification is subject to change without further notice.
7.2.11 RA (PLL, Main Clock Selection, Watchdog Timer),
Counter3 Data
a) PAGE 0 (PLL Enable Bit, Main Clock Selection Bits,
Watchdog Timer Enable Bit)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IDLE
PLLEN
CLK2
CLK1
CLK0
-
-
WDTEN
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
Bit 0 (WDTEN)
:
Watch dog control bit
You can use WDTC instruction to clear watch dog counter. The counter
clock source is 32768/2 Hz. If the prescaler is assigned to TCC, Watch dog
will time out by (1/32768 )*2 * 256 = 15.616mS. If the prescaler is assigned
to WDT, the time out interval will be longer depending on the prescaler.
Ratio.
0/1
disable/enable
Bit 1~Bit 2
:
Unused
Bit 3 ~ Bit 5 (CLK0 ~ CLK2)
:
MAIN clock selection bits
You can select different frequencies for the main clock with CLK1 and
CLK2. All the available clock selections are listed below.
PLLEN
CLK2
CLK1
CLK0
Sub clock
MAIN clock
CPU clock
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
447.829kHz
895.658kHz
1.791MHz
3.582MHz
7.165MHz
10.747MHz
14.331MHz
17.91MHz
Don’t care
447.829kHz (Normal mode)
895.658kHz (Normal mode)
1.791MHz (Normal mode)
3.582MHz (Normal mode)
7.165MHz (Normal mode)
10.747MHz (Normal mode)
14.331MHz (Normal mode)
17.91MHz (Normal mode)
32.768kHz (Green mode)
Don’t care Don’t care Don’t care
Bit 6 (PLLEN)
:
PLL's power control bit which is CPU mode control register
0/1
disable PLL/enable PLL
If PLL is enabled, CPU will operate at normal mode (high frequency).
Otherwise, it will run at green mode (low frequency, 32768 Hz).
Sub-clock
32.768kHz
switch
0
1
System clock
PLL circuit
447.8293kHz ~17.9132MHz
ENPLL
CLK2 ~ CLK0
Fig. 6 The Relation Between 32.768kHz and PLL
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