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參數(shù)資料
| 型號(hào)： | EM78P5830AAM |
| 廠商： | ELAN Microelctronics Corp . |
| 英文描述： | 8-BIT MICRO-CONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 15/43頁 |
| 文件大小： | 396K |
| 代理商： | EM78P5830AAM |
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EM785830AA
8-bit Micro-controller
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
12/1/2004 V1.6
Bit 6 (PWM1E): PWM1 enable bit
0
PWM1 is off (default value), and its related pin carries out the PC1 function;
1
PWM1 is on, and its related pin will be set to output automatically.
Bit 7 (PWM2E): PWM2 enable bit
0
PWM2 is off (default value), and its related pin carries out the PC2 function.
1
PWM2 is on, and its related pin will be set to output automatically.
R6 (PORT6 I/O data, SPI data buffer)
PAGE0 (PORT6 I/O data register)
7
6
5
4
P67
P66
P65
P64
R/W
R/W
R/W
R/W
Bit0 ~Bit1: Unused register. These two bits are not allowed to use.
Bit2 ~ Bit7 (P62 ~ P67) : 6-bit PORT6(2~7) I/O data register
User can use IOC register to define input or output each bit.
PAGE1 : (undefined) not allowed to use
PAGE2 (SPI data buffer)
7
6
5
4
SPIB7
SPIB6
SPIB5
SPIB4
R/W
R/W
R/W
R/W
Bit 0 ~ Bit 7 (SPIB0 ~ SPIB7) : SPI data buffer
If you write data to this register, the data will write to SPIW register. If you read this data, it will read the
data from SPIR register. Please refer to figure7
PAGE3 (DT1L: the Least Significant Byte ( Bit 7 ~ Bit 0) of Duty Cycle of PWM1)
7
6
5
4
3
PWM1[7] PWM1[6] PWM1[5] PWM1[4] PWM1[3] PWM1[2] PWM1[1] PWM1[0]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
A specified value keeps the output of PWM1 to stay at high until the value matches with TMR1.
R7 (PORT7 I/O data, Data RAM bank)
PAGE0 (PORT7 I/O data register)
7
6
5
4
3
X
P76
P75
P74
P73
-
R/W
R/W
R/W
R/W
Bit 0 ; Bit3 ~ Bit 7 (P73 ~ P76) : 5-bit PORT7 I/O data register
User can use IOC register to define input or output each bit.
Bit1~2, Bit 7: Unused register. These three bits are not allowed to use.
PAGE1 (Data RAM bank selection bits)
7
6
5
4
3
-
-
AD9
AD8
R
R
-
Bit 0(RAM_B0) : Data RAM bank selection bits
Each bank has address 0 ~ address 255 which is total 256 (0.25k) bytes RAM size.
Data RAM bank selection : (Total RAM = 0.5K)
RAM_B0
RAM bank
0
Bank0
1
Bank1
Bit 1 : (undefined) not allowed to use. This bit must clear to 0.
3
2
1
X
-
0
X
-
P63
R/W
P62
R/W
3
2
1
0
SPIB3
R/W
SPIB2
R/W
SPIB1
R/W
SPIB0
R/W
2
1
0
R/W-0
R/W-0
R/W-0
2
X
-
1
X
-
0
P70
R/W
2
1
0
0
ADRES
R/W-0
RAM_B0
R/W-0
R/W-0
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