
15
* This specification are subject to be changed without notice.
9.30.1997
EM78810
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the
interrupts (when enabled) generated, will cause the next instruction to be fetched from address 008H. Once in
the interrupt service routine the source of the interrupt can be determined by polling the flag bits in the RF register.
The interrupt flag bit must be cleared in software before leaving the interrupt service routine and enabling
interrupts to avoid recursive interrupts.
There are four external interrupt pins including INT0 , INT1 , INT2 , INT3 . The INT2 and INT3 sent to the same
interrupt flag . And four internal counter interrupt available.
External interrupt INT0 , INT1 , INT2 , INT3 signals are from PORT5 bit0 to bit3 . If IOCF is enable then these
signal will cause interrupt , or these signals will be treated as general input data .
After resetting, the next instruction will be fetched from address 000H, and the software interrupt is 001H and
the hardware interrupt is 008H.
Instruction Set
(1). Every bit of any register can be set, cleared, or tested directly.
(2). The I/O register can be regarded as general register. That is, the same instruction can operates on I/O
register.
The symbol “R” represents a register designator which specifies which one of the 64 registers (including
operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4
determine the selected register bank. “b’’ represents a bit field designator which selects the number of the bit,
located in the register “R’’, affected by the operation. “k’’ represents an 8 or 10-bit constant or literal value.
INSTRUCTION BINARY
HEX
MNEMONIC
OPERATION
STATUS
AFFECTED
None
C
None
T,P
T,P
None
None
None
None
0
0
0
0
0
0
0
0
0
0
0000 0000 0000
0000 0001 0001
0000 0000 0010
0000 0000 0011
0000 0000 0100
0000 0000 rrrr
0000 0001 0000
0000 0001 0001
0000 0001 0010
0000 0001 0011
0000
0001
0002
0003
0004
000r
0010
0011
0012
0013
NOP
DAA
CONTW
SLEP
WDTC
IOW R
ENI
DISI
RET
RETI
No Operation
Decimal Adjust A
A
→
CONT
0
→
WDT, Stop oscillator
0
→
WDT
A
→
IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack]
→
PC
[Top of Stack]
→
PC
Enable Interrupt
CONT
→
A
IOCR
→
A
R2+A
→
R2 bits 9,10
do not clear
A
→
R
0
→
A
0
→
R
R-A
→
A
R-A
→
R
R-1
→
A
R-1
→
R
None
None
None
0
0
0
0000 0001 0100
0000 0001 rrrr
0000 0010 0000
0014
001r
0020
CONTR
IOR R
TBL
Z,C,DC
None
Z
Z
Z,C,DC
Z,C,DC
Z
Z
0
0
0
0
0
0
0
0000 01rr
0000 1000 0000
0000 11rr
0001 00rr
0001 01rr
0001 10rr
0001 11rr
rrrr
00rr
0080
00rr
01rr
01rr
01rr
01rr
MOV R,A
CLRA
CLR R
SUB A,R
SUB R,A
DECA R
DEC R
rrrr
rrrr
rrrr
rrrr
rrrr