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參數(shù)資料
| 型號： | EM65160 |
| 英文描述： | Synchronous Rectified MOSFET Driver; Temperature Range: -40°C to 85°C; Package: 8-QFN |
| 中文描述： | 圖形STN液晶顯示器驅(qū)動 |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 726K |
| 代理商： | EM65160 |
EM65160
160 COM/SEG Dot Matrix LCD Driver
* This specification are subject to be changed without notice.
6/27/2002 (V1.1)
6
Data Latch
In case of segment mode, latches the data on the data bus. The latched state of each LCD driver output pin is controlled by the
control logic and the data latch control, 160 bits of data are read in 20 sets of 8 bits.
Line Latch / Shift Register
In case of segment mode, all 160 bits, which have been read into the data latch block are simultaneously latched on the falling
edge of the LP signal, and output to the level shifter block.
In case of common mode, shifts data from the data input pin on the falling edge of the LP signal.
Level Shifter
The logic voltage signal is boost to the LCD driver voltage level, and output to the driver block.
4-level Driver
Drive the LCD driver output pins from the line latch/shift register data, selecting one of 4 levels (V0, V12, V43, VSS) based on
the S/C, FR and /DSPOF
Clock control Logic
Controls the operation of each block. In case of segment mode, when a LP signal has been input, all blocks are reset and the
control logic waits for the selection signal output from the active control block.
Once the selection signal has been output, operation of the data latch and data transmission are controlled, 160 bits of data are
read in, and the chip is deselected. In case of common mode, controls the direction of data shift.
Relation between FR, data input and Liquid crystal display driver output voltage level, Explain as following table 4:
Table-4 Liquid Crystal Display Driver Output Voltage Level (Segment Mode)
(a) Segment Mode
FR
Latch data
/DSPOF
Driver output voltage level
H
V0
H
L
H
V2
L
H
VSS
L
H
V3
X
L
VSS
VSS < V43< V12< V0
H: VDD
L: VSS
X: Don’t
care
(b) Common Mode
FR
Latch data
/DSPOF
Driver output voltage level
H
VSS
H
L
H
V1
L
H
V0
L
H
V4
X
L
VSS
VSS < V43< V12< V0
H:VDD, L:VSS , X: Don’t care
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