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參數(shù)資料
| 型號： | EM65160 |
| 英文描述： | Synchronous Rectified MOSFET Driver; Temperature Range: -40°C to 85°C; Package: 8-QFN |
| 中文描述： | 圖形STN液晶顯示器驅(qū)動(dòng) |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 726K |
| 代理商： | EM65160 |
EM65160
160 COM/SEG Dot Matrix LCD Driver
* This specification are subject to be changed without notice.
6/27/2002 (V1.1)
5
Common Mode (Continuous)
Symbol
I/O
Connected to
Functions
DIR
I
Controller
Directional selection of bi-directional shift register
DIR
Data read direction
L
Y160 to Y1
H
Y1 to Y160
/DSPOF
I
Controller
Control signal for output deselect level
˙
The input signal is level-shifted from logic voltage level to LCD driver voltage level，and
controls LCD drive circuit
˙
When the signal is low，the output (Y1 – Y160) of LCD drive be set to level VSS，the
contents of shift register are reset not read
˙
When this signal return to high, the operation returns to the normal status.
FR
I
Controller
AC signal for LCD drive
˙
Input a frame inversion signal
˙
The LCD driver output voltage level can be set by line latch output signal and FR signal
MD
I
Vss/VDD
Mode selection
MD
Mode selection
H
Dual mode
L
Single mode
S/C
I
Vss/VDD
Selection of segment mode/common mode
S/C
Mode selection
H
Segment mode
L
Common mode
DI7
I
Controller
Dual mode data input
˙
In dual mode，data can input from 81st bit
DI0-DI6
I
VSS or VDD
Not used, avoiding floating.
XCK
I
VSS or open
Not used
Y1-Y160
O
LCD Panel
LCD driver output.
˙
One of four voltage levels is output according to FR signal and the data of shift register
FUNCTIONAL DESCRIPTIONS
Active Control
In case of segment mode, controls the selection or de-selection of the chip. Following a LP signal, and after the chip select
signal is input, a select signal is generated internally until 160bits of data have been read in. Once data input has been
completed, a select signal for cascade connection is output, and the chip is deselected. In case of common mode, controls the
input/output data of bi-directional pins.
SP Conversion & Data Control
In case of segment mode, keep input data which are 2 clocks of XCK at 4-bit parallel mode into latch circuit, or keep input
data which are 1 clock of XCK at 8-bits parallel mode into latch circuit, after that they are put on the internal data bus 8 bits at
a time.
Data Latch Control
In case of segment mode, selects the state of the data latch which reads in the data bus signals. The shift direction is controlled
by the control logic, for every 16 bits of data read in, the selection signal shifts one bit based on the state of the control circuit.
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