參數(shù)資料
型號(hào)： EM65160
英文描述： Synchronous Rectified MOSFET Driver; Temperature Range: -40°C to 85°C; Package: 8-QFN
中文描述： 圖形STN液晶顯示器驅(qū)動(dòng)
文件頁(yè)數(shù)： 15/20頁(yè)
文件大?。?/td> 726K
代理商： EM65160
EM65160
160 COM/SEG Dot Matrix LCD Driver
* This specification are subject to be changed without notice.
6/27/2002 (V1.1)
4
Segment mode (continuous)
Symbol
I/O
Connected to
Functions
/DSPOF
I
Controller
Control signal for output deselect level
˙
The input signal is level-shifted from logic voltage level to LCD driver voltage level ，and
controls LCD drive circuit
˙
When the signal is low，the output (Y1 – Y160) of LCD drive be set to level VSS，the
contents of line latch are reset，but read the display data in the data latch regardless of
condition of /DSPOF
˙
When this signal is high, the operation returns to the normal status.
FR
I
Controller
AC signal for LCD drive
˙
Input a frame inversion signal
˙
The LCD driver output voltage level can be set by line latch output signal and FR signal
Mode selection
MD
Mode selection
H
8-bit parallel input
L
4-bit parallel input
MD
I
VSS/VDD
Input/output for chip selection
˙
In output state，after 160-bit of data have been read，set to “L” then set to “H”
˙
In input state ，the chip is selected when EI is set to “L”，then 160-bit of data have been
read，the chip is deselected
DIR
EIO1
EIO2
H
Input
Output
L
Output
Input
EIO1，EIO2
I
Y1-Y160
O
LCD Panel
LCD driver output.
One of four levels is output according to the combination of the FR signal and display data
Common Mode
Table-3 Pin Functions Of Common Mode
Symbol
I/O
Connected to
Functions
VDD
I
Power supply
Power supply for internal logic connects to +2.5 to +5.5V
VSS
I
GND
Connect to Ground
V0R, V0L
V12R, V12L
V34R, V34L
I
Power supply
Power supply for LCD driver level
˙
Normally，the bias voltage used is set by resistor divider
˙
Ensure that the voltage are set such that
0
12
43
V
<
ss
˙
To further reduce the difference between the output waveforms of LCD driver output pin
Y1 and Y160 ,externally connect ViR and ViL (i=0,12,34)
EIO1，EIO2
I
Data input/output shift for bi-directional shift register
˙
When EIO1(EIO2) is input，it will be pull-down
˙
When EIO1(EIO2) is output，it will not be pull-down
DIR
EIO1
EIO2
H
Input
Output
L
Output
Input
LP
I
Controller
Shift clock for bi-directional shift register
˙
Data is shifted on the falling edge of the clock
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