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參數(shù)資料
| 型號： | EM65160 |
| 英文描述： | Synchronous Rectified MOSFET Driver; Temperature Range: -40°C to 85°C; Package: 8-QFN |
| 中文描述： | 圖形STN液晶顯示器驅(qū)動 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 726K |
| 代理商： | EM65160 |
EM65160
160 COM/SEG Dot Matrix LCD Driver
* This specification are subject to be changed without notice.
6/27/2002 (V1.1)
3
PIN DESCRIPTION
Table-1 Pin Arrangement
Pin NO.
Symbol
I/O
Description
1 to 160
Y1 -Y160
O
LCD driver output
161,186
VOL, VOR
-
Power supply for LCD driver
162,185
V12L, V12R
-
Power supply for LCD driver
163,184
V43L, V43R
-
Power supply for LCD driver
165
DIR
I
Display data shift direction selection
166
VDD
-
Power supply for logic system
167
S/C
I
Segment/common mode selection
168
180
EIO2
EIO1
I/O
Input /output for chip select or data of shift register
169 to 176
DI0 – DI7
DI7
I
Display data input for segment mode
Dual mode data input for common mode
177
XCK
I
Display data shift clock input for segment mode
178
/DSPOF
I
Control input for deselect output level
179
LP
I
Latch pulse input/shift clock input for shift register
181
FR
I
AC-converting signal input for LCD driver waveform
182
MD
I
Mode selection input
164,183
VSS
-
Ground (0 V)
Segment Mode
Table-2 Pin Functions Of Segment Mode
Symbol
I/O
Connected to
Functions
VDD
I
Power Supply
Power supply for internal logic connects to +2.5 to +5.5V
VSS
I
GND
Connect to Ground
V0R，V0L
V12R，V12L
V43R，V43L
I
Power Supply
Power supply for LCD driver level
˙
Normally，the bias voltage used is set by resistor divider
˙
Ensure that the voltage are set such that
0
12
43
V
<
ss
˙
To further reduce the difference between the output waveforms of LCD driver output pin
Y1 and Y160，externally connect ViR and ViL (i=0,12,43)
DI0 – DI7
I
Controller
Input for display data
˙
In 4-bit parallel input mode，input data into DI0 – DI3, connect DI4 – DI7 to VSS or VDD
˙
In 8-bit parallel input mode，input data into DI0 – DI7
XCK
I
Controller
Clock signal for taking display data
Data is read on the falling of the clock pulse
LP
I
Controller
Latch signal for display data
˙
Data is latched on the falling edge of the clock pulse
Selection of segment mode/common mode
S/C
Mode selection
H
Segment mode
L
Common mode
S/C
I
VSS/VDD
Directional selection for reading display data
DIR
Data read direction
L
Y160 to Y1
H
Y1 to Y160
DIR
I
VSS/VDD
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