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參數(shù)資料
| 型號(hào)： | EM48AM3244VBA-7FE |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 256Mb (2Mⅴ4Bankⅴ32) Synchronous DRAM |
| 中文描述： | 256Mb的（200萬(wàn)ⅴ4Bankⅴ32）同步DRAM |
| 文件頁(yè)數(shù)： | 3/17頁(yè) |
| 文件大?。?/td> | 208K |
| 代理商： | EM48AM3244VBA-7FE |
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eorex
EM488M3244VBA
Jul. 2006
www.eorex.com
3/17
Pin Description (Simplified)
Pin
Name
Function
J1
CLK
(System Clock)
Master clock input (Active on the positive rising edge)
(Chip Select)
Selects chip when active
(Clock Enable)
Activates the CLK when
“
H
”
and deactivates when
“
L
”
.
CKE should be enabled at least one cycle prior to new
command. Disable input buffers for power down in standby.
(Address)
Row address (A0 to A11) is determined by A0 to A11 level at
the bank active command cycle CLK rising edge.
CA (CA0 to CA8) is determined by A0 to A8 level at the read or
write command cycle CLK rising edge.
And this column address becomes burst access start address.
A10 defines the pre-charge mode. When A10= High at the
pre-charge command cycle, all banks are pre-charged.
But when A10= Low at the pre-charge command cycle, only the
bank that is selected by BA is pre-charged.
(Bank Address)
Selects which bank is to be active.
(Row Address Strobe)
Latches Row Addresses on the positive rising edge of the CLK
with /RAS
“
L
”
. Enables row access & pre-charge.
(Column Address Strobe)
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
(Write Enable)
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
(Data Input/Output Mask)
DQM controls I/O buffers.
J8
/CS
J2
CKE
G8,G9,F7,F3,G1,
G2,G3,H1,H2,J3,
G7,H9
A0~A11
J7,H8
BA0,BA1
J9
/RAS
K7
/CAS
K8
/WE
K9,K1,F8,F2
DQM0~DQM3
R8,N7,R9,N8,P9,
M8,M7,L8,L2,M3,
M2,P1,N2,R1,N3,
R2,E8,D7,D8,B9,
C8,A9,C7,A8,A2,
C3,A1,C2,B1,D2,
D3,E2
A7,F9,L7,R7/
A3,F1,L3,R3
B2,B7,C9,D9,E1,
L1,M9,N9,P2/B8,
B3,C1,D1,E9,L9,
M1,N1,P8
DQ0~DQ31
(Data Input/Output)
DQ pins have the same function as I/O pins on a conventional
DRAM.
V
DD
/V
SS
(Power Supply/Ground)
V
DD
and V
SS
are power supply pins for internal circuits.
V
DDQ
/V
SSQ
(Power Supply/Ground)
V
DDQ
and V
SSQ
are power supply pins for the output buffers.
E3,E7,H3,H7,K2,
K3
NC
(No Connection)
This pin is recommended to be left No Connection on the
device.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EM48AM3244VBA-8FE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Mb (2M′4Bank′32) Synchronous DRAM |
| EM48AM3244VBB-75FE | 制造商:EOREX 制造商全稱:EOREX 功能描述:256Mb (2M】4Bank】32) Synchronous DRAM |
| EM48AM3244VBB-7FE | 制造商:EOREX 制造商全稱:EOREX 功能描述:256Mb (2M】4Bank】32) Synchronous DRAM |
| EM48AM3244VBB-8FE | 制造商:EOREX 制造商全稱:EOREX 功能描述:256Mb (2M】4Bank】32) Synchronous DRAM |
| EM48AM3244VBC-75FE | 制造商:EOREX 制造商全稱:EOREX 功能描述:256Mb (2M】4Bank】32) Synchronous DRAM |
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