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參數(shù)資料
| 型號(hào)： | EDI8F81027C |
| 英文描述： | 1Mx8 CMOS SRAM Monolithic(1Mx8 CMOS單片靜態(tài)RAM) |
| 中文描述： | 1Mx8 CMOS SRAM的單片（1Mx8的CMOS單片靜態(tài)內(nèi)存） |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大小： | 114K |
| 代理商： | EDI8F81027C |
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI8F81027C
A-18
W
A19
E
DQ-7
DECODER
September 1999 Rev. 2; ECO #11933
1Mx8 CMOS SRAM MONOLITHIC
FEATURES
s 1 Meg x 8 bit CMOS Static
s Random Access Memory
Access Times 55 thru 100ns
Data Retention Function (EDI8F81027LP )
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
s High Density Packaging
32 Pin DIP, No.
s Single +5V (
±10%) Supply Operation
FIG. 1
PIN CONFIGURATION
TOP VIEW
DESCRIPTION
The EDI8F81027C is an 8 megabit CMOS Static RAM based on
two 512Kx8 Static RAMs mounted on a multi-layered epoxy
laminate (FR4) substrate.
A low power version with data retention (EDI8F81027LP) is
also available.
All inputs and outputs are TTL compatible and operate from a
single 5V supply.
Fully asynchronous, the EDI8F81027C requires no clocks or
refreshing for operation.
PIN DESCRIPTION
A-19
Address Inputs
E
Chip Enable
W
Write Enable
DQ-7
Common Data
Input/Output
VCC
Power (+5V
±10%)
VSS
Ground
NC
No Connection
BLOCK DIAGRAM
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A
DQ
DQ1
DQ2
VSS
32 VCC
31 A15
30 A17
29 W
28 A13
27 A8
26 A9
25 A11
24 A19
23 A10
22 E
21 DQ7
20 DQ6
19 DQ5
18 DQ4
17 DQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
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