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參數(shù)資料
| 型號(hào)： | EBJ21UE8BFU0-DJ-F |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 256M X 64 DDR DRAM MODULE, ZMA204 |
| 封裝： | HALOGEN FREE AND ROHS COMPLIANT, SODIMM-204 |
| 文件頁(yè)數(shù)： | 1/16頁(yè) |
| 文件大小： | 240K |
| 代理商： | EBJ21UE8BFU0-DJ-F |
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Document No. E1642E30 (Ver. 3.0)
Date Published August 2010 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2010
DATA SHEET
2GB DDR3 SDRAM SO-DIMM
EBJ21UE8BFU0 (256M words
× 64 bits, 2 Ranks)
Specifications
Density: 2GB
Organization
256M words × 64 bits, 2 ranks
Mounting 16 pieces of 1G bits DDR3 SDRAM sealed
in FBGA
Package: 204-pin socket type small outline dual in
line memory module (SO-DIMM)
PCB height: 30.0mm
Lead pitch: 0.6mm
Lead-free (RoHS compliant) and Halogen-free
Power supply: VDD = 1.5V ± 0.075V
Data rate: 1600Mbps/1333Mbps (max.)
Backward compatible to1066Mbps/800Mbps/667Mbps
Eight internal banks for concurrent operation
(components)
Interface: SSTL_15
Burst lengths (BL): 8 and 4 with Burst Chop (BC)
/CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11
/CAS write latency (CWL): 5, 6, 7, 8
Precharge: auto precharge option for each burst
access
Refresh: auto-refresh, self-refresh
Refresh cycles
Average refresh period
7.8
s at 0°C ≤ TC ≤ +85°C
3.9
s at +85°C < TC ≤ +95°C
Operating case temperature range
TC = 0°C to +95°C
Features
Double-data-rate architecture; two data transfers per
clock cycle
The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for
better command and data bus efficiency
On-Die-Termination (ODT) for better signal quality
Synchronous ODT
Dynamic ODT
Asynchronous ODT
Multi Purpose Register (MPR) for pre-defined pattern
read out
ZQ calibration for DQ drive and ODT
Programmable Partial Array Self-Refresh (PASR)
/RESET pin for Power-up sequence and reset
function
SRT range:
Normal/extended
Programmable Output driver impedance control
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EBJ41UF8BAS0-GN-F | 1G X 64 DDR DRAM MODULE, ZMA204 |
| EC11.0001.001 | Power Entry Module; IEC; Voltage Rating: 250V; Current Rating: 20A; Terminal Type: Quick Connect Tabs; Appliance inlet with line switch; 2-pole; single elements are already wired |
| EC11.0001.201 | Power Entry Module; IEC; Voltage Rating: 250V; Current Rating: 20A; Terminal Type: Quick Connect Tabs; Appliance inlet with line switch; 2-pole; single elements are already wired |
| EC11.0001.301 | Power Entry Module; IEC; Voltage Rating: 250V; Current Rating: 20A; Terminal Type: Quick Connect Tabs; Appliance inlet with line switch; 2-pole; single elements are already wired |
| EC11.0001.401 | Power Entry Module; IEC; Voltage Rating: 250V; Current Rating: 20A; Terminal Type: Quick Connect Tabs; Appliance inlet with line switch; 2-pole; single elements are already wired |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EBJ21UE8BFU0-GL-F | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB DDR3 SDRAM SO-DIMM |
| EBJ21UE8BFU0-GN-F | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB DDR3 SDRAM SO-DIMM |
| EBJ21UE8BFU1 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB DDR3 SDRAM SO-DIMM |
| EBJ21UE8BFU1-DJ-F | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB DDR3 SDRAM SO-DIMM |
| EBJ24A | 制造商:ADAM-TECH 制造商全稱:Adam Technologies, Inc. 功能描述:EURO BLOCKS TS & EB SERIES |
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