
22
56F801 Technical Data
Figure 11. Connecting an External Clock Signal
Figure 12. External Clock Timing
3.5.4
An internal relaxation oscillator can supply the reference frequency when an external frequency source or
crystal are not used. During a 56F801 boot or reset sequence, the relaxation oscillator is enabled by default,
and the PRECS bit in the PLLCR word is set to 0 (
Section 3.5
). If an external oscillator is connected, the
relaxation oscillator can be deselected instead by setting the PRECS bit in the PLLCR to 1. When this
occurs, the PRECSS bit in the PLLSR (prescaler clock select status register) data word also sets to 1. If a
changeover between internal and external oscillators is required at startup, internal device circuits
compensate for any asynchronous transitions between the two clock signals so that no glitches occur in the
resulting master clock to the chip. When changing clocks, the user must ensure that the clock source is not
switched until the desired clock is enabled and stable.
Use of On-Chip Relaxation Oscillator
To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator
can be incrementally adjusted to within
±0.
25% of 8MHz by trimming an internal capacitor. Bits 0-7 of the
IOSCTL (internal oscillator control) word allow the user to set in an additional offset (trim) to this preset
value to increase or decrease capacitance. The default value of this trim is 128 units, making the power-up
default capacitor size 432 units. Each unit added or deleted changes the output frequency by about 0.2%,
allowing incremental adjustment until the desired frequency accuracy is achieved.
Table 21. External Clock Operation Timing Requirements
3
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40
°
to +85
°
C
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation (external clock driver)
1
1.
2.
3.
4.
See
Figure 11
for details on using the recommended connection of an external clock driver.
May not exceed 60MHz for the DSP56F801FA60 device.
The high or low pulse width must be no smaller than 6.25ns or the chip will not function.
Parameters listed are guaranteed by design.
f
osc
0
—
80
2
MHz
Clock Pulse Width
3, 4
t
PW
6.25
—
—
ns
56F801
XTAL
EXTAL
External Clock
V
SS
External
Clock
V
IH
V
IL
Note: The midpoint is V
IL
+ (V
IH
– V
IL
)/2.
90%
50%
10%
90%
50%
10%
t
PW
t
PW
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.