參數(shù)資料
型號(hào)： DS3148N
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 44/89頁(yè)
文件大?。?/td> 0K
描述： IC 8CH DS3/3 FRAMER 349-BGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
控制器類型： DS3/E3 調(diào)幀器
接口： LIU
電源電壓： 3.135 V ~ 3.465 V
電流 - 電源： 640mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 349-BGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 349-HCBGA（27x27）
包裝： 托盤
DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
49 of 89
Register Name:
BCR4
Register Description:
BERT Control Register 4
Register Address:
33h
Bit #
7
6
5
4
3
2
1
0
Name
AWC7
AWC6
AWC5
AWC4
AWC3
AWC2
AWC1
AWC0
Default
0
Bits 0 to 7: Alternating Word Count Rate (AWC[7:0]). When the BERT is programmed in the alternating word
mode, it transmits the word in register RP[15:0] a number of times equal to AWC[7:0] + 1 and then transmits the
word loaded in RP[31:16] the same number of times. The valid count range is from 00h to FFh. These bits are
ignored if the BERT is programmed for a pseudorandom pattern or a repetitive pattern.
AWC VALUE
ALTERNATING COUNT ACTION
00h
Send the word in RP[15:0] 1 time followed by the word in RP[31:16] 1 time…
01h
Send the word in RP[15:0] 2 times followed by the word in RP[31:16] 2 times…
02h
Send the word in RP[15:0] 3 times followed by the word in RP[31:16] 3 times…
.
FFh
Send the word in RP[15:0] 256 times followed by the word in RP[31:16] 256 times…
Register Name:
BSR
Register Description:
BERT Status Register
Register Address:
38h
Bit #
7
6
5
4
3
2
1
0
Name
N/A
RA1
RA0
N/A
BBCO
BECO
SYNC
Default
—
Bit 0: Synchronization Status (SYNC). This real-time status bit is set when the incoming pattern matches for 32
consecutive bit positions. SYNC bit is cleared when six or more bits out of 64 are received in error.
Bit 1: BERT Error-Counter Overflow (BECO). This real-time status bit is set when the 24-bit BERT error counter
(BEC) saturates. BECO is cleared when BCR1:LC is toggled to load the error counts.
Bit 2: BERT Bit-Counter Overflow (BBCO). This real-time status bit is set when the 32-bit BERT bit counter
(BBC) saturates. BBCO is cleared when BCR1:LC is toggled to load the error counts.
Bit 4: Receive All Zeros (RA0). This real-time status bit is set when 32 consecutive 0s are received. RA0 is
cleared when a 1 is received.
Bit 5: Receive All Ones (RA1). This real-time status bit is set when 32 consecutive 1s are received. RA1 is
cleared when a 0 is received.
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