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參數(shù)資料
| 型號： | DS3148N |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 29/89頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 8CH DS3/3 FRAMER 349-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 控制器類型： | DS3/E3 調(diào)幀器 |
| 接口： | LIU |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 電流 - 電源： | 640mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 349-BGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 349-HCBGA（27x27） |
| 包裝： | 托盤 |
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DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
35 of 89
Register Name:
T3E3CR2
Register Description:
DS3/E3 Control Register
Register Address:
11h
Bit #
7
6
5
4
3
2
1
0
Name
FRESYNC
N/A
TFEBE
AFEBED
ECC
FECC1
FECC0
E3CVE
Default
0
—
0
Bit 0: E3 Code Violation Enable (E3CVE). This bit is ignored in the DS3 mode. In E3 mode, this bit is used to
configure the bipolar violation count register (BPVCR1) to count either bipolar violations (BPV) or code violations
(CV). A BPV is defined as consecutive pulses (or marks) of the same polarity that are not part of an HDB3
codeword. A CV is defined in ITU O.161 as consecutive BPVs of the same polarity.
0 = count BPVs
1 = count CVs
Bits 1, 2: Frame Error-Counting Control (FECC[1:0])
FECC[1:0]
FRAME ERROR-COUNT REGISTER (FECR1) CONFIGURATION
00
DS3 Mode: Count OOF occurrences
E3 Mode: Count OOF occurrences
01
DS3 Mode: Count both F-bit and M-bit errors
E3 Mode: Count bit errors in the FAS word
10
DS3 Mode: Count only F-bit errors
E3 Mode: Count word errors in the FAS word
11
DS3 Mode: Count only M-bit errors
E3 Mode: Illegal state
Bit 3: Error-Counting Control (ECC). This bit is used to control whether the framer increments certain error
counters during OOF conditions. It only affects the error counters that deal with framing overhead:
Frame Error-Count Register (FECR1) (when it is configured to count frame errors, not OOFs)
DS3 P-Bit Parity Error-Count Register (PCR1)
DS3 CP-Bit Parity Error-Count Register (CPCR1)
DS3 Far-End Block Error-Count Register (FEBECR1)
When this bit is logic 0, these error counters are not allowed to increment during OOF conditions. When this bit is
logic 1, these error counters are allowed to increment during OOF conditions.
0 = do not allow the FECR/PCR/CPCR/FEBECR error counters to increment during OOF
1 = allow the FECR/PCR/CPCR/FEBECR error counters to increment during OOF
Bit 4: Automatic FEBE Defeat (AFEBED). This bit is ignored in E3 mode and in M23 DS3 mode. When this bit is
low, the framer automatically inserts FEBE codes into the transmit data stream by setting all three C bits in M-
subframe 4 to logic 0. A FEBE condition occurs when any received M bits or F bits are in error, or when the
received CP bits indicate a parity error or when the receiver is in the OOF condition.
0 = automatically insert FEBE codes in the transmit data stream based on detected errors
1 = use the TFEBE control to determine the state of the FEBE codes
Bit 5: Transmit FEBE Setting (TFEBE). This bit is only active when AFEBED is logic 1. When this bit is logic 0,
the formatter forces the FEBE code to 111. When this bit is set logic 1, the formatter forces the FEBE code to 000.
0 = force FEBE to 111 (null state)
1 = force FEBE to 000 (active state)
Bit 7: Force Receive Framer Resynchronization (FRESYNC). A 0-to-1 transition on this bit causes the receive
framer to resynchronize. This bit must be cleared and set again for a subsequent resynchronization to occur.
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