參數(shù)資料
型號： DS31412
廠商： Maxim Integrated Products
文件頁數(shù)： 9/89頁
文件大?。?/td> 0K
描述： IC 12CH DS3/3 FRAMER 349-BGA
標(biāo)準(zhǔn)包裝： 1
控制器類型： DS3/E3 調(diào)幀器
接口： LIU
電源電壓： 3.135 V ~ 3.465 V
電流 - 電源： 960mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 349-BGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 349-HCBGA（27x27）
包裝： 托盤
DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
17 of 89
6.1 Status Register Description
There are two types of bits used to build the status and information registers. The real-time status register bit
indicates the state of the corresponding signal at the time it was read. The latched status register bit is set when
the corresponding signal changes state (low-to-high, high-to-low, or both, depending on the bit). The latched status
bit is cleared when written with logic 1 and is not set again until the corresponding signal changes state again.
The following is example host-processor pseudocode that checks to see if the BERT SYNC status has changed:
If ((BSRL and 01h) neq 0) then
// SYNCL bit is set
BSRL = 01h
// Clear SYNCL bit only
If ((BSR and 01h) neq 0) then
// BERT has changed to in sync
–––––
Else
// BERT has changed to out of sync
–––––
There are four suffixes used for status and information register names: SR for real-time status registers, SRL for
latched status registers, SRIE for interrupt-enable registers, and IR for information registers. Latched status bits
have the suffix “L” and interrupt-enable bits have the suffix “IE.” The bits in the SR, SRL, and SRIE registers are
arranged such that related real-time status, latched status, and interrupt-enable bits are located in the same bit
position in neighboring registers. For example, Table 6-B shows that the real-time status bit SYNC, the latched
status bit SYNCL, and the interrupt-enable bit SYNCIE are all located in bit 0 of their respective registers (BSR,
BSRL, and BSRIE).
When set, most latched status register bits can cause an interrupt on the
INT pin if the corresponding interrupt-
enable register bit is also set. Most latched status register bits have an associated real-time status register bit.
Information registers can contain a mix of real-time and latched status bits, none of which can cause an interrupt.
Table 6-B. Status Register Set Example
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
N/A
RA1
RA0
N/A
BBCO
BECO
SYNC
N/A
RA1L
RA0L
BEDL
BBCOL
BECOL
SYNCL
N/A
BEDIE
BBCOIE
BECOIE
SYNCIE
Figure 6-1. Status Register Interrupt Flow
WR
EVENT
LATCHED STATUS REGISTER
SET ON EVENT DETECT
CLEAR ON WRITE LOGIC 1
INT ENABLE
REGISTER
SR
SRL
INT
OTHER INT
SOURCE
REAL-TIME STATUS
LATCHED STATUS
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參數(shù)描述
DS31412N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12 Port DS3/E3 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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