參數(shù)資料
型號(hào)： DS31412
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 65/89頁(yè)
文件大?。?/td> 0K
描述： IC 12CH DS3/3 FRAMER 349-BGA
標(biāo)準(zhǔn)包裝： 1
控制器類型： DS3/E3 調(diào)幀器
接口： LIU
電源電壓： 3.135 V ~ 3.465 V
電流 - 電源： 960mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 349-BGA 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 349-HCBGA（27x27）
包裝： 托盤(pán)
DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
68 of 89
8. OPERATION DETAILS
8.1 Reset
The DS314x devices must be reset by activating the
JTRST and RST pins after the power supply has settled and
the input clocks have stabilized to their normal operating conditions. The
JTRST pin can be permanently wired low
if desired. After reset, all read/write control register bits are reset to 0 except for RDATH and TUA1, which are set
to 1. The reset states of the device pins are as follows:
E3 mode is enabled.
The LIU interface is in dual-rail (POS/NEG) mode with HDB3 encoding and decoding enabled.
TPOS and TNEG transmit an unframed all-ones signal (E3 AIS) on the transmit LIU interface.
RDAT is forced to a logic 1 level to present an unframed all-ones signal (E3 AIS) on the receive system
interface.
TCLK is a noninverted, delayed version of TICLK.
ROCLK is a noninverted, delayed version or RCLK.
TSOF is an active-high input pin.
RSOF, RLOS, and ROOF are active high.
TDEN/TGCLK is in the TDEN (data enable) mode and is active high.
RDEN/RGCLK is in the RDEN (data enable) mode and is active high.
JTDO is tri-stated.
8.2 DS3 and E3 Mode Configuration
In all modes, the TUA1 bit in the MC1 register and RDATH bit in the MC4 register must be cleared. These bits are
set to 1 at reset to generate an unframed all-ones (E3 AIS) signal on both the transmit LIU interface (TPOS/TNEG)
and the receive system interface (RDAT).
E3 Mode
Default framer operation after reset is E3 mode. To begin operation in E3 mode after reset, clear the TUA1 bit in
the MC1 register and clear the RDATH bit in the MC4 register. A 34.368MHz clock must be applied to the TICLK
pin.
DS3 M23 Mode
To change framer operation after reset to DS3 M23 mode, set the DS3M bit to 1 in the T3E3CR1 register, clear the
TUA1 bit in the MC1 register, and clear the RDATH bit in the MC4 register. A 44.736MHz clock must be applied to
the TICLK pin.
DS3 C-Bit Parity Mode
To change framer operation after reset to DS3 C-Bit Parity mode, set the DS3M and CBEN bits to 1 in the
T3E3CR1 register, clear the TUA1 bit in the MC1 register, and clear the RDATH bit in the MC4 register. A
44.736MHz clock must be applied to the TICLK pin.
8.3 LIU and System Interface Configuration
LIU Interface
After reset the default LIU interface format is dual-rail (POS/NEG) with B3ZS/HDB3 encoding and decoding
enabled. To change framer operation after reset to binary (NRZ) format with B3ZS/HDB3 encoding and decoding
disabled (disabled in the framer but should be enabled in the LIU), set the BIN bit to 1 in the MC1 register.
System Interface
After reset the TDEN/TGCLK and RDEN/RGCLK pins default to data enable behavior (TDEN, RDEN) and the
TSOF pin defaults to being an input. If gapped clock behavior is desired, set the TDENMS bit tin the MC3 register
and/or the RDENMS bit in the MC4 register. To configure TSOF as an output pin, set the TSOFC bit to 1 in the
MC3 register.
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