參數(shù)資料
型號: DS31412
廠商: Maxim Integrated Products
文件頁數(shù): 63/89頁
文件大?。?/td> 0K
描述: IC 12CH DS3/3 FRAMER 349-BGA
標準包裝: 1
控制器類型: DS3/E3 調(diào)幀器
接口: LIU
電源電壓: 3.135 V ~ 3.465 V
電流 - 電源: 960mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 349-BGA 裸露焊盤
供應商設備封裝: 349-HCBGA(27x27)
包裝: 托盤
DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
66 of 89
Register Name:
FSRIE
Register Description:
FEAC Status Register Interrupt Enable
Register Address:
63h
Bit #
7
6
5
4
3
2
1
0
Name
N/A
RFFOIE
RFFNIE
RFIIE
RFCDIE
TFIIE
Default
0
Bit 0: Transmit FEAC Idle Interrupt Enable (TFIIE). This bit enables an interrupt if the TFIL bit in the FSRL
register is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 1: Receive FEAC Codeword Detected Interrupt Enable (RFCDIE). This bit enables an interrupt if the RFCDL
bit in the FSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 2: Receive FEAC Idle Interrupt Enable (RFIIE). This bit enables an interrupt if the RFIL bit in the FSRL
register is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 3: Receive FEAC FIFO Not-Empty Interrupt Enable (RFFNIE). This bit enables an interrupt if the RFFNL bit
in the FSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 4: Receive FEAC FIFO Overflow Interrupt Enable (RFFOIE). This bit enables an interrupt if the RFFOL bit in
the FSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
Figure 7-8. FEAC Status Bit Interrupt Signal Flow
POS EDGE
DETECT
LATCH
NEG EDGE
DETECT
LATCH
POS EDGE
DETECT
LATCH
FSRL.RFIL
FSRL.RFFNL
FSRL.RFFOL
FSRIE.RFIIE
FSRIE.RFFNIE
FRSIE.RFFOIE
POS EDGE
DETECT
LATCH
FSRL.TFIL
FSRIE.TFIIE
FSR.TFI
TRANSMIT FEAC
IDLE STATE
RECEIVER IN
IDLE STATE
RECEIVE FIFO
EMPTY
RECEIVE FIFO
OVERFLOW
DETECTED
INT PIN (ORed
WITH OTHER
SOURCES)
MSRIE.FEACIE
MSR.FEAC
FSR.RFI
FSR.RFFE
POS EDGE
DETECT
LATCH
FSRL.RFCDL
FSRIE.RFCDIE
FSR.RFCD
RECEIVE
CODE WORD
DETECTED
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