參數(shù)資料
型號(hào)： DS2483R+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 27/29頁(yè)
文件大小： 0K
描述： IC I2C TO 1WIRE BRIDGE SOT23-6
產(chǎn)品培訓(xùn)模塊： Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
系列： *
7
Maxim Integrated
DS2483
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
Active Pullup (APU)
The APU bit controls whether an active pullup (low
impedance transistor) or a passive pullup (RWPU resis-
tor) is used to drive a 1-Wire line from low to high. When
APU = 0, active pullup is disabled (resistor mode).
Enabling active pullup is generally recommended for
best 1-Wire bus performance. The active pullup does
not apply to the rising edge of a recovery after a short
on the 1-Wire line. If enabled, a fixed-duration active
pullup (typically 2.5Fs standard speed, 0.5Fs overdrive
speed) also applies in a reset/presence detect cycle on
the rising edges after tRSTL and after tPDL.
The circuit that controls rising edges operates as follows
(Figure 2): At t1, the pulldown (from DS2483 or 1-Wire
slave) ends. From this point on the 1-Wire bus is pulled
high through RWPU internal to the DS2483. VCC and the
capacitive load of the 1-Wire line determine the slope. In
case that active pullup is disabled (APU = 0), the resis-
tive pullup continues, as represented by the solid line.
With active pullup enabled (APU = 1), and when at t2 the
voltage has reached the VIAPO threshold, the DS2483
activates a low-impedance pullup transistor, as repre-
sented by the dashed line. The active pullup remains
active until the end of the time slot (t3), after which the
resistive pullup continues. The shortest duration of the
active pullup is tREC0 - (t2 - t1) in a write-zero time slot
and the longest duration is tW0L + tREC0 - tW1L - (t2 -
t1) in a write-one time slot. In a read-data time slot, the
active pullup duration is slave dependent. See the Strong
Pullup (SPU) section for a way to keep the pullup transis-
tor conducting beyond t3.
1-Wire Power Down (PDN)
The PDN bit is used to remove power from the 1-Wire
port, e.g., to force a 1-Wire slave to perform a power-on
reset. PDN can as well be used in conjunction with the
sleep mode (see Table 2 for details). While PDN is 1,
no 1-Wire communication is possible. To end the 1-Wire
power-down state, the PDN bit must be changed to 0.
Note: When writing to the device configuration register
with PDN = 1 to activate the 1-Wire power-down mode,
make sure that the SPU bit is 0.
Table 2. Effects of PDN and SLPZ
Figure 2. Rising Edge Pullup as Seen at the End of a Write-Zero Time Slot
PDN =
SLPZ IS LOGIC 0
SLPZ IS LOGIC 1
0
RWPU is connected.
IOisatVCC, keeping the slaves powered.
TheDS2483ispowereddown(sleepmode).
RWPU is connected.
IOisatVCC, keeping the slaves powered.
TheDS2483ispoweredup(normaloperation).
1
RWPU is disconnected.
IOisat0V,causingtheslavestolosepower.
TheDS2483ispowereddown(sleepmode).
RWPU is disconnected.
IOisat0V,causingtheslavestolosepower.
TheDS2483ispoweredup.
APU = 0
NEXT TIME SLOT
APU = 1
VCC
0V
1-Wire BUS IS
DISCHARGED
t1
t2
t3
VIAPO
VIL1MAX
tREC0
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