參數(shù)資料
型號(hào)： DS21Q42TN
廠商： Maxim Integrated Products
文件頁數(shù)： 78/116頁
文件大?。?/td> 0K
描述： IC FRAMER ENHANCED T1 4X 128TQFP
標(biāo)準(zhǔn)包裝： 72
控制器類型： T1 調(diào)幀器
接口： 并行/串行
電源電壓： 2.97 V ~ 3.63 V
電流 - 電源： 75mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-LQFP（14x20）
包裝： 管件
DS21Q42
64 of 116
SYMBOL
POSITION
NAME AND DESCRIPTION
TZSD
HCR.1
Transmit Zero Stuffer Defeat. Overrides internal enable.
0 = enable the zero stuffer (normal operation)
1 = disable the zero stuffer
TCRCD
HCR.0
Transmit CRC Defeat.
0 = enable CRC generation (normal operation)
1 = disable CRC generation
HSR: HDLC STATUS REGISTER (Address = 01 Hex)
(MSB)
(LSB)
RBOC
RPE
RPS
RHALF
RNE
THALF
TNF
TMEND
SYMBOL
POSITION
NAME AND DESCRIPTION
RBOC
HSR.7
Receive BOC Detector Change of State. Set whenever the
BOC detector sees a change of state from a BOC Detected to a
No Valid Code seen or vice versa. The setting of this bit prompt
the user to read the RBOC register for details.
RPE
HSR.6
Receive Packet End. Set when the HDLC controller detects
either the finish of a valid message (i.e., CRC check complete)
or when the controller has experienced a message fault such as a
CRC checking error, or an overrun condition, or an abort has
been seen. The setting of this bit prompts the user to read the
RHIR register for details.
RPS
HSR.5
Receive Packet Start. Set when the HDLC controller detects an
opening byte. The setting of this bit prompts the user to read the
RHIR register for details.
RHALF
HSR.4
Receive FIFO Half Full. Set when the receive 64–byte FIFO
fills beyond the half way point. The setting of this bit prompts
the user to read the RHIR register for details.
RNE
HSR.3
Receive FIFO Not Empty. Set when the receive 64–byte FIFO
has at least one byte available for a read. The setting of this bit
prompts the user to read the RHIR register for details.
THALF
HSR.2
Transmit FIFO Half Empty. Set when the transmit 64–byte
FIFO empties beyond the half way point. The setting of this bit
prompts the user to read the THIR register for details.
TNF
HSR.1
Transmit FIFO Not Full. Set when the transmit 64–byte FIFO
has at least one byte available. The setting of this bit prompts
the user to read the THIR register for details.
TMEND
HSR.0
Transmit Message End. Set when the transmit HDLC
controller has finished sending a message. The setting of this bit
prompts the user to read the THIR register for details.
Note: The RBOC, RPE, RPS, and TMEND bits are latched and are cleared when read.
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